HARDWARE-ASSISTED DESIGN VERIFICATION SYSTEM USING

专利名称：HARDWARE-ASSISTED DESIGN

VERIFICATION SYSTEM USING A PACKET-BASED PROTOCOL LOGIC SYNTHESIZEDFOR EFFICIENT DATA LOADING ANDUNLOADING

发明人：OHKAMI, Takahide申请号：EP01271071.1申请日：20011019公开号：EP1399858A2公开日：20040324

摘要：The design that system prvided increases the user in the register and memoryof accessibility carries out the design verification system of functionality verificationinhardware auxiliary. Packet-based agreement is loaded onto register and memory forexecuting the day of year accelerator between the work station of data transferoperation and host and having unloaded data, target design (DUV) logic simulationduring verifying. The target DUV that this method and equipment complex interface logicare provided into DUV in preferably access register and memory carries out simulationand ancillary hardware accelerator.

申请人：Quickturn Design Systems, Inc.

地址：2655 Seeley Avenue,Building 5 San Jose, California 95134 US

国籍：US

代理机构：Viering, Jentschura & Partner

更多信息请下载全文后查看