CY28405-3资料

CY28405-3

Clock Synthesizer with Differential SRC and CPU Outputs

Features

•Supports Intel£ Pentium® 4-type CPUs•Selectable CPU frequencies•3.3V power supply •Nine copies of PCI clocks

•Four copies of 3V66 with one optional VCH•Two copies 48 MHz clock•Two copies of REF

CPUx 3SRCx 13V66x 4PCIx 9REFx 248Mx 2•Three differential CPU clock pairs•One differential SRC clock

•Support SMBus/I2C Byte, Word and Block Read/ Write•Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction•48-pin SSOP package

Block DiagramXINXOUTPin ConfigurationVDD_REFREF(0:1)[1]XTALOSCPLL 1 PLL Ref FreqDividerNetworkVDD_CPUCPUT(0:1, ITP), CPUC(0:1, ITP)VDD_SRCTSRCT, SRCCFS_(A:B)VTT_PWRGD#IREFVDD_3V663V66_(0:2)PLL22VDD_PCIPCIF(0:2)PCI(0:5)3V66_3/VCHVDD_48MHzDOT_48USB_48PD#SDATASCLKI2CLogic*FS_A/REF_0*FS_B/REF_1VDD_REFXINXOUTVSS_REFPCIF0PCIF1PCIF2VDD_PCIVSS_PCIPCI0PCI1PCI2PCI3VDD_PCIVSS_PCIPCI4PCI5PD#DOT_48USB_48VSS_48VDD_48123456710111213141516171819202122232448474443424140393837363534333231302928272625VDDAVSSAIREFCPUT_ITPCPUC_ITPVSS_CPUCPUT1CPUC1VDD_CPUCPUT0CPUC0VSS_SRCSRCTSRCCVDD_SRCVTT_PWRGD#SDATA*SCLK*3V66_03V66_1VSS_3V66VDD_3V663V66_23V66_3/VCH~SSOP-48* 100k Internal Pull-upNote:

1.Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.

CY28405-3Rev1.0,November 22, 2006

2200 Laurelwood Road, Santa Clara, CA 950

Tel:(408) 855-0555

Fax:(408) 855-0550

Page 1 of 16

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CY28405-3Pin Description

Pin No.

Name

Type

Description

124

FS_A/REF_0FS_B/REF_1XIN

I/O, SEI/O, SEI

This pin is the FS_A at power-up and VTT_PWRGD# = 0, then it becomes REF_0 output. (3.3V 14.318-MHz clock output.)

This pin is the FS_B at power up and VTT_PWRGD# = 0, then it becomes REF_1 output. (3.3V 14.318-MHz clock output.)

Crystal connection or external reference frequency input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input.

Crystal connection.Connection for an external 14.318-MHz crystal output.

CPU clock output.Differential CPU clock outputs. See Table1 for frequency configuration.

539, 42,38, 41,45, 4436, 3526, 29, 30257, 8, 9

XOUTCPUT(0:1),CPUC(0:1), CPUT_ITP, CPUC_ITPSRCT, SRCC3V66(2:0)3V66_3/VCHPCI_F(0:2)

O, SEO, DIF

O, DIFO, SEO, SEO, SEO, SEO, SEO, SEII, PUII/O, PUI, PUPWRGNDPWRGND

Differential serial reference clock.

66 MHz clock output.3.3V 66 MHz clock from internal VCO.48 or 66 MHz clock output. 3.3V selectable through SMBUS to be 66 MHz or 48 MHz. Default is 66 MHz.

Free-running PCI Output.33 MHz clocks divided down from 3V66.PCI Clock Output.33 MHz clocks divided down from 3V66.Fixed 48 MHz clock output.Fixed 48MHz clock output.

Current Reference.A precision resistor is attached to this pin which is connected to the internal current reference.3.3V LVTTL input for PowerDown# active low.

3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E] input (active low).SMBus-compatible SDATA.SMBus-compatible SCLOCK.3.3V power supply for PLL.Ground for PLL.

3.3V power supply for outputs.Ground for outputs.

12, 13, 14, 15, 18, PCI(0:5)19222146203332314847

3, 10, 16, 24, 27, 34, 40

6, 11, 17, 23, 28, 37, 43

USB_48DOT_48IREFPD#

VTT_PWRGD#SDATASCLKVDDAVSSAVDDVSS

Frequency Select Pins (FS_A, FS_B)

Host clock frequency selection is achieved by applying theappropriate logic levels to FS_A and FS_B inputs prior toVTT_PWRGD# assertion (as seen by the clock synthesizer).Upon VTT_PWRGD# being sampled low by the clock chip(indicating processor VTT voltage is stable), the clock chipsamples the FS_A & FS_B input values. For all logic levels ofFS_A and FS_B VTT_PWRGD# employs a one-shot function-ality in that once a valid low on VTT_PWRGD# has beensampled low, all further VTT_PWRGD#, FS_A, and FS_Btransitions will be ignored. Once “Test Clock Mode” has beeninvoked, all further FS_B transitions will be ignored and FS_Awill asynchronously select between the Hi-Z and REF/N mode.Exiting test mode is accomplished by cycling power with FS_Bin a high or low state.

Rev 1.0,November 22, 2006Page 2 of 16

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CY28405-3Table 1.Frequency Select Table (FS_A FS_B) FS_A00011

FS_B0B6b710B6b7

CPU100 MHzREF/N200 MHz133 MHzHi-Z

SRC100/200 MHzREF/N100/200 MHz100/200 MHz

Hi-Z

3V6666 MHzREF/N66 MHz66 MHzHi-Z

PCIF/PCI33 MHzREF/N33 MHz33 MHzHi-Z

REF014.3 MHzREF/N14.3 MHz14.3 MHzHi-Z

REF114.31 MHzREF/N14.31 MHz14.31 MHzHi-Z

USB/DOT48 MHzREF/N48 MHz48 MHzHi-Z

Table 2.Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1FS_A001

FS_B010

CPU200 MHz400 MHz266 MHz

SRC100/200 MHz100/200 MHz100/200 MHz

3V6666 MHz66 MHz66 MHz

PCIF/PCI33 MHz33 MHz33 MHz

REF014.3 MHz14.3 MHz14.3 MHz

REF114.31 MHz14.31 MHz14.31 MHz

USB/DOT48 MHz48 MHz48 MHz

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,a two-signal serial interface is provided. Through the SerialData Interface, various device functions, such as individualclock output buffers, can be individually enabled or disabled.The registers associated with the Serial Data Interfaceinitializes to their default setting upon power-up, and thereforeuse of this interface is optional. Clock device register changesare normally made upon system initialization, if any arerequired. The interface cannot be used during systemoperation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,block write, and block read operations from the controller. Forblock write/read operation, the bytes must be accessed insequential order from lowest to highest byte (most significantbit first) with the ability to stop after any complete byte hasbeen transferred. For byte write and byte read operations, thesystem controller can access individually indexed bytes. Theoffset of the indexed byte is encoded in the command code,as described in Table3.

The block write and block read protocol is outlined in Table4while Table5 outlines the corresponding byte write and byteread protocol. The slave receiver address is 11010010 (D2h).

Table 3.Command Code Definition

Bit7(6:0)

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 4. Block Read and Block Write Protocol

Block Write Protocol

Bit12:1011:181920:272829:363738:46

Start

Slave address – 7 bitsWrite = 0

Acknowledge from slave

Command Code – 8 bits

'00000000' stands for block operationAcknowledge from slaveByte Count – 8 bitsAcknowledge from slaveData byte 1 – 8 bitsAcknowledge from slaveData byte 2 – 8 bitsAcknowledge from slave

Description

Bit12:1011:18192021:27282930:3738

Start

Slave address – 7 bitsWrite = 0

Acknowledge from slave

Command Code – 8 bits

'00000000' stands for block operationAcknowledge from slaveRepeat start

Slave address – 7 bitsRead = 1

Acknowledge from slaveByte count from slave – 8 bitsAcknowledge from master

Block Read Protocol

Description

Rev 1.0,November 22, 2006Page 3 of 16

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CY28405-3Table 4. Block Read and Block Write Protocol (continued)

Block Write Protocol

Bit.... ....

....

............

......................

Data Byte (N–1) –8 bitsAcknowledge from slaveData Byte N –8 bitsAcknowledge from slaveStop

Description

Bit39:4748:5556............

Table 5.Byte Read and Byte Write protocol

Byte Write Protocol

Bit12:1011:18

Start

Slave address – 7 bitsWrite = 0

Acknowledge from slave

Command Code – 8 bits

'100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed

Acknowledge from slaveData byte from master – 8 bitsAcknowledge from slaveStop

Description

Bit12:1011:18

Start

Slave address – 7 bitsWrite = 0

Acknowledge from slave

Command Code – 8 bits

'100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessedAcknowledge from slaveRepeat start

Slave address – 7 bitsRead = 1

Acknowledge from slaveData byte from slave – 8 bitsAcknowledge from masterStop

Byte Read Protocol

Description

Block Read Protocol

Description

Data byte from slave – 8 bitsAcknowledge from masterData byte from slave – 8 bitsAcknowledge from masterData byte N from slave – 8 bitsAcknowledge from masterStop

1920:272829

192021:27282930:373839

Byte Configuration Map

Byte 0: Control Register

Bit 76

01

@Pup

ReservedPCIFPCIReservedReserved ReservedReservedFS_BFS_A

Name

Reserved, set = 0

PCI Drive Strength Override

0 = Force All PCI and PCIF Outputs to Low Drive Strength1 = Force All PCI and PCIF Outputs to High Drive StrengthReserved, set = 0 Reserved, set = 0Reserved, set = 1Reserved, set = 1

Power up latched value of FS_B pinPower up latched value of FS_A pin

Description

3210

0011HWHW

Rev 1.0,November 22, 2006Page 4 of 16

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CY28405-3Byte 1: Control Register

Bit763210

01111111

@Pup

SRCTSRCCSRCTSRCCReservedReservedReserved

CPUT_ITP, CPUC_ITPCPUT1, CPUC1CPUT0, CPUC0

Name

Description

Allow control of SRC during SW PCI_STP assertion0 = Free Running, 1 = Stopped with SW PCI_STPSRC Output Enable

0 = Disabled (three-state), 1 = EnabledReserved, set = 1Reserved, set = 1Reserved, set = 1

CPU_ITP Output Enable

0 = Disabled (three-state), 1 = EnabledCPU(T/C)1 Output Enable,

0 = Disabled (three-state), 1 = EnabledCPUT/C)0 Output Enable

0 = Disabled (three-state), 1 = Enabled

Byte 2: Control Register

Bit763210

00000000

@Pup

Name

SRCT, SRCCSRCT, SRCC

CPUT_ITP, CPUC_ITPCPUT1, CPUC1CPUT0, CPUC0ReservedReservedReserved

Description

SRCT/C Pwrdwn drive mode

0 = Driven in power down, 1 = three-state in power down SRC Stop drive mode

0 = Driven in PCI_STP, 1 = three-state in power downCPU(T/C)_ITP Pwrdwn drive mode

0 = Driven in power down, 1 = three-state in power downCPU(T/C)1 Pwrdwn drive mode

0 = Driven in power down, 1 = three-state in power downCPU(T/C)0 Pwrdwn drive mode

0 = Driven in power down, 1 = three-state in power downReserved, set = 0Reserved, set = 0Reserved, set = 0

Byte 3: Control Register

Bit7

1

@Pup

Name

SW PCI STOP

Description

SW PCI_STP Function

0= PCI_STP assert, 1= PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will resume in a synchronous manner with no short pulses.Reserved

PCI5 Output Enable

0 = Disabled, 1 = EnabledPCI4 Output Enable

0 = Disabled, 1 = EnabledPCI3 Output Enable

0 = Disabled, 1 = EnabledPCI2 Output Enable

0 = Disabled, 1 = EnabledPCI1 Output Enable

0 = Disabled, 1 = EnabledPCI0 Output Enable

0 = Disabled, 1 = Enabled

63210

1111111

ReservedPCI5PCI4PCI3PCI2PCI1PCI0

Rev 1.0,November 22, 2006Page 5 of 16

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CY28405-3Byte 4: Control RegisterBit763210

01000111

@Pup

USB_48USB_48PCIF2PCIF1PCIF0PCIF2PCIF1PCIF0

Name

Description

USB_48MHz Drive Strength Control

0 = Low Drive Strength, 1 = High Drive StrengthUSB_48MHz Output Enable0 = Disabled, 1 = Enabled

Allow control of PCIF2 with assertion of SW PCI_STP0 = Free Running, 1 = Stopped with SW PCI_STPAllow control of PCIF1 with assertion of SW PCI_STP0 = Free Running, 1 = Stopped with SW PCI_STPAllow control of PCIF0 with assertion of SW PCI_STP0 = Free Running, 1 = Stopped with SW PCI_STPPCIF2 Output Enable

0 = Disabled, 1 = EnabledPCIF1 Output Enable

0 = Disabled, 1 = EnabledPCIF0 Output Enable

0 = Disabled, 1 = Enabled

Byte 5: Control Register

Bit763210

11011111

@Pup

DOT_48Reserved3V66_3/VCH3V66_3/VCHReserved3V66_23V66_13V66_0

Name

DOT_48MHz Output Enable0 = Disabled, 1 = EnabledReserved

3V66_3/VCH Frequency Select

0 = 3V66 mode, 1 = VCH (48MHz) mode3V66_3/VCH Output Enable0 = Disabled, 1 = EnabledReserved, set = 13V66_2 Output Enable0 = Disabled, 1 = Enabled3V66_1 Output Enable0 = Disabled, 1 = Enabled3V66_0 Output Enable0 = Disabled, 1 = Enabled

Description

Byte 6: Control Register

Bit765

000

@Pup

Reserved

CPUC0, CPUT0CPUC1, CPUT1

CPUT_ITP,CPUC_ITPSRCT, SRCCPCIFPCI3V66

SRCT,SRCC

CPUT_ITP,CPUC_ITP

Name

Reserved

Reserved, set = 0Reserved, set = 0FS_A & FS_B Operation0 = Normal, 1 = Test modeSRCT/C Frequency Select0 = 100Mhz, 1 = 200MHzSpread Spectrum Mode

0 = down (default), 1 = center

Description

43

00

Rev 1.0,November 22, 2006Page 6 of 16

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CY28405-3Byte 6: Control Register (continued)

Bit2

0

@Pup

Name

PCIFPCI3V66

SRCT,SRCC

CPUT_ITP,CPUC_ITPREF_1REF_0

Description

Spread Spectrum Enable

0 = Spread Off, 1 = Spread On

10

11

REF_1 Output Enable0 = Disabled, 1 = EnabledREF_0 Output Enable0 = Disabled, 1 = Enabled

Byte 7: Control Register

Bit763210

01001000

@Pup

Name

Revision ID Bit 3Revision ID Bit 2Revision ID Bit 1Revision ID Bit 0Vendor ID Bit 3Vendor ID Bit 2Vendor ID Bit 1Vendor ID Bit 0

Description

Revision ID Bit 3Revision ID Bit 2Revision ID Bit 1Revision ID Bit 0Vendor ID Bit 3Vendor ID Bit 2Vendor ID Bit 1Vendor ID Bit 0

Crystal Recommendations

The CY28405-3 requires a Parallel Resonance Crystal.Substituting a series resonance crystal will cause theCY28405-3 to operate at the wrong frequency and violate theppm specification. For most applications there is a 300-ppmfrequency shift between series and parallel crystals due toincorrect loading.

Table 6.Crystal Recommendations

Frequency (Fund)14.31818 MHz

CutAT

LoadingLoad CapParallel

20 pF

Drive(max.)0.1 mW

Shunt Cap Motional (max.)(max.)5 pF

0.016 pF

Tolerance

(max.)50 ppm

Stability (max.)50 ppm

Aging(max.)5 ppm

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-mance. To realize low ppm performance, the total capacitancethe crystal will see must be considered to calculate the appro-priate capacitive loading (CL).

The following diagram shows a typical crystal configurationusing the two trim capacitors. An important clarification for thefollowing discussion is that the trim capacitors are in serieswith the crystal not parallel. It’s a common misconception thatload capacitors are in parallel with the crystal and should beapproximately equal to the load capacitance of the crystal.This is not true.

Figure 1. Crystal Capacitive Clarification

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CY28405-3Calculating Load Capacitors

In addition to the standard external trim capacitors, tracecapacitance and pin capacitance must also be considered tocorrectly calculate crystal loading. As mentioned previously,the capacitance on each side of the crystal is in series with thecrystal. This means the total capacitance on each side of thecrystal must be twice the specified crystal load capacitance(CL). While the capacitance on each side of the crystal is inseries with the crystal, trim capacitors (Ce1,Ce2) should becalculated to provide equal capacitive loading on both sides.

Clock Chip(CY28405-2)Ci1Ci2Pin3 to 6pCs1X1X2Cs2Trace2.8pFXTALCe1Ce2Trim33pFFigure 2. Crystal Loading ExampleUse the following formulas to calculate the trim capacitorvalues from Ce1 and Ce2.

Load Capacitance (each side)

Ce = 2 * CL - (Cs + Ci)

CLe

Total Capacitance (as seen by the crystal)

=

1(Ce1 + Cs1 + Ci11

+

1Ce2 + Cs2 + Ci2)

CL...................................................Crystal load capacitanceCLe.........................................Actual loading seen by crystal......................................using standard value trim capacitorsCe.....................................................External trim capacitorsCs.............................................Stray capacitance (trace,etc)Ci .............Internal capacitance (lead frame, bond wires etc)

is low, all clocks are driven to a LOW value and held there andthe VCO and PLLs are also powered down. All clocks are shutdown in a synchronous manner so has not to cause glitcheswhile transitioning to the low ‘stopped’ state.PD# – Assertion

When PD# is sampled low by two consecutive rising edges ofCPUC clock then all clock outputs (except CPU) clocks mustbe held low on their next high to low transition. CPU clocksmust be hold with CPU clock pin driven high with a value of 2xIref and CPUC undriven.

Due to the state of itnernal logic, stopping and holding the REFclock outputs in the LOW state may require more than oneclock cycle to complete

PD# (Power-down) Clarification

The PD# (Power Down) pin is used to shut off ALL clocks priorto shutting off power to the device. PD# is an asynchronousactive LOW input. This signal is synchronized internally to thedevice powering down the clock synthesizer. PD# is anasynchronous function for powering up the system. When PD#

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CY28405-3PD#CPUT, 133MHzCPUC, 133MHzSRCT 100MHzSRCC 100MHz3V66, 66MHzUSB, 48MHzPCI, 33MHzREF, 14.31818Figure 3. Power-down Assertion Timing Waveforms

PD# Deassertion

The power-up latency between PD# rising to a valid logic ‘1’level and the starting of all clocks is less than 3.0 ms.

Tstable<1.8nSPD#CPUT, 133MHzCPUC, 133MHzSRCT 100MHzSRCC 100MHz3V66, 66MHzUSB, 48MHzPCI, 33MHzREF, 14.31818Tdrive_PWRDN#<300PS, >200mVFigure 4. Power-down Deassertion Timing Waveforms

Rev 1.0,November 22, 2006Page 9 of 16

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CY28405-3FS_A, FS_BVTT_PWRGD#PWRGD_VRMVDD Clock GenClock StateState 00.2-0.3mSDelayState 1Wait forVTT_PWRGD#Sample SelsState 2State 3OnDevice is not affected,VTT_PWRGD# is ignoredClock OutputsOffOnClock VCOOffFigure 5. VTT_PWRGD# Timing Diagram

S1S2VTT_PWRGD# = LowDelay>0.25mSVDD_A = 2.0VSampleInputs strapsWait for <1.8msS0S3VDD_A = offPower OffNormalOperationVTT_PWRGD# = toggleEnable OutputsFigure 6. Clock Generator Power-up/Run State Diagram

Rev 1.0,November 22, 2006Page 10 of 16

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CY28405-3Absolute Maximum Conditions

ParameterVDDVDDAVINTSTATJESDHBMØJCØJAUL–94MSL

Description

Core Supply VoltageAnalog Supply VoltageInput VoltageTemperature, Storage

Temperature, Operating AmbientTemperature, Junction

ESD Protection (Human Body Model)Dissipation, Junction to CaseDissipation, Junction to AmbientFlammability RatingMoisture Sensitivity Level

Relative to V SSNon-functionalFunctionalFunctional

MIL-STD-883, Method 3015Mil-Spec 883E Method 1012.1JEDEC (JESD 51) At 1/8 in.

Condition

Min.–0.5–0.5–0.5–650–2000

36.983.5V–01

Max.4..6VDD + 0.5+15070150–

UnitVVVDC°C°C°CV°C/W°C/W

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

ParameterVDD, VDDAVILI2CVIHI2CVILVIHIILIILI2CVOLVOHIOZCINCOUTLINVXIHVXILIDDIPD

Description

3.3 Operating VoltageInput Low VoltageInput High VoltageInput Low VoltageInput High VoltageInput Leakage Current Forward Bias CurrentOutput Low VoltageOutput High Voltage

High-Impedance Output CurrentInput Pin CapacitanceOutput Pin CapacitancePin InductanceXin High VoltageXin Low VoltageDynamic Supply CurrentPower-down Supply Current

At 200 MHz and all outputs loaded per Table9 and Figure7PD# asserted, all differential outputs three-stated.Except SDATA and SCLKexcept Pull ups or Pull downs0 < VIN < VDD

VDD = OFF, SCLK and SDATA at 0V or 3.3VIOL = 1 mA IOH = –1 mA3.3V ± 5%SDATA, SCLKSDATA, SCLK

Condition

Min.3.135–2.2VSS–0.52.0–5–5–2.4–1023–0.7VDD

0––

Max.3.4651.0–0.8VDD+0. 5

550.4–10567VDD0.3VDD3502

UnitVVVVVµAµAVVµApFpFnHVVmAmA

Rev 1.0,November 22, 2006Page 11 of 16

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CY28405-3AC Electrical Specifications

ParameterCrystalTDCDescriptionXIN Duty CycleConditionThe device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specifi-cationWhen Xin is driven from an external clock sourceMeasured between 0.3VDD and 0.7VDDAs an average over 1-PsdurationOver 150 msMeasured at crossing point VOXMeasured at crossing point VOXMeasured at crossing point VOXMeasured at crossing point VOXMeasured at crossing point VOXMeasured at crossing point VOXMeasured from Vol = 0.175 to Voh = 0.525VDetermined as a fraction of 2*(TR-TF)/(TR+TF)459.99707.49784.9985––175–––Math averages Figure 7Math averages Figure 7660–150250––0.3See Figure 7. Measure SE Measured at crossing point VOXMeasured at crossing point VOXMeasured at crossing point VOXMeasured at crossing point VOXMeasured at crossing point VOXMeasured from Vol= 0.175 to Voh = 0.525VDetermined as a fraction of 2*(TR-TF)/(TR+TF)–459.99704.9985––175–––Math averages Figure 7Math averages Figure 7660–150250Min.47.5Max.52.5Unit%TPERIODTR / TFTCCJLACCCPU at 0.7VTDCTPERIODTPERIODTPERIODTSKEWTCCJTR / TFTRFM'TR'TFVHIGHVLOWVOXVOVSVUDSVRBSRCTDCTPERIODTPERIODLACCTCCJTR / TFTRFM'TR'TFVHIGHVLOWVOXXIN periodXIN Rise and Fall TimesXIN Cycle to Cycle JitterLong-term AccuracyCPUT and CPUC Duty Cycle100-MHz CPUT and CPUC Period133-MHz CPUT and CPUC Period200-MHz CPUT and CPUC PeriodAny CPUT/C to CPUT/C Clock Skew CPUT/C Cycle to Cycle JitterCPUT and CPUC Rise and Fall TimesRise/Fall MatchingRise Time VariationFall Time VariationVoltage HighVoltage LowCrossing Point Voltage at 0.7V SwingMaximum Overshoot VoltageMinimum Undershoot VoltageRing Back VoltageSRCT and SRCC Duty Cycle100 MHz SRCT and SRCC Period200 MHz SRCT and SRCC PeriodLong Term AccuracySRCT/C Cycle to Cycle JitterSRCT and SRCC Rise and Fall TimesRise/Fall MatchingRise Time VariationFall Time VariationVoltage HighVoltage LowCrossing Point Voltage at 0.7V Swing69.841––71.010.05003005510.0037.50235.001510012570020125125850–550VHIGH + 0.3–0.25510.0035.001530012570020125125850–550nsnspsppm%nsnsnspspsps%pspsmVmVmVVVV%nsnsppmpsps%pspsmvmvmVRev 1.0,November 22, 2006Page 12 of 16

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CY28405-3AC Electrical Specifications (continued)

ParameterVOVSVUDSVRB3V66TDCTPERIODTPERIODTHIGHTLOWTR / TFTSKEWTCCJPCI/PCIFTDCTPERIODTPERIODTHIGHTLOWTR / TFTSKEWTCCJDOTTDCTPERIODTHIGHTLOWTR / TFTCCJTSKEWUSBTDCTPERIODTHIGHTLOWTR / TFTCCJTSKEWREFTDCTPERIODTR / TFDescriptionMaximum Overshoot VoltageMinimum Undershoot VoltageRing Back Voltage3V66 Duty CycleSpread Disabled 3V66 PeriodSpread Enabled 3V66 Period3V66 High Time3V66 Low Time3V66 Rise and Fall TimesAny 3V66 to Any 3V66 Clock Skew3V66 Cycle-to-Cycle JitterPCI Duty CycleSpread Disabled PCIF/PCI PeriodSpread Enabled PCIF/PCI PeriodPCIF and PCI High TimePCIF and PCI Low TimePCIF and PCI Rise and Fall TimesSee Figure 7. Measure SEMeasurement at 1.5VMeasurement at 1.5VMeasurement at 1.5VMeasurement at 2.0VMeasurement at 0.8VMeasured between 0.8V and 2.0VMeasurement at 1.5VMeasurement at 1.5VMeasurement at 1.5VMeasurement at 1.5VMeasurement at 1.5VMeasurement at 2.0VMeasurement at 0.8VMeasured between 0.8V and 2.0VMeasurement at 1.5VMeasurement at 1.5VMeasurement at 1.5VMeasurement at 2.0VMeasurement at 0.8VMeasured between 0.8V and 2.0VMeasurement at 1.5VMeasurement @1.5VMeasurement at 1.5VMeasurement at 1.5VMeasurement at 2.0VMeasurement at 0.8VMeasured between 0.8V and 2.0VMeasurement at 1.5VMeasurement @1.5VMeasurement at 1.5VMeasurement at 1.5VMeasured between 0.8V and 2.0VConditionMin.––0.3–4514.995514.995.95004.55000.5––4529.991029.991012.012.00.5––4520.82718.0947.6941.0––4520.82718.0947.6941.0––4569.8271.0Max.VHIGH + 0.3–0.25515.004515.0799––2.02502505530.000930.1598––2.05002505520.839610.0369.8362.03505005520.839610.0369.8362.03505005569.85.0UnitVVV%nsnsnsnsnspsps%nsnsnsnsnspsps%nsnsnsnspsps%nsnsnsnspsps%nsV/nsAny PCI clock to Any PCI Clock Skew Measurement at 1.5VPCIF and PCI Cycle to Cycle JitterDuty CyclePeriod USB High TimeUSB Low TimeRise and Fall TimesCycle to Cycle JitterAny 48 MHz to 48 MHz clock skewDuty CyclePeriod USB High TimeUSB Low TimeRise and Fall TimesCycle to Cycle JitterAny 48 MHz to 48 MHz Clock SkewREF Duty CycleREF Period REF Rise and Fall TimesRev 1.0,November 22, 2006Page 13 of 16

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CY28405-3AC Electrical Specifications (continued)

ParameterTCCJTSKEWDescriptionREF Cycle to Cycle JitterAny REF to REF clock skewConditionMeasurement at 1.5VMeasurement @1.5VMin.–––10.00Max.10005001.8––UnitpspsmsnsnsENABLE/DISABLE and SET-UPTSTABLEClock Stabilization from Power-upTSSTSHStopclock Set-up TimeStopclock Hold TimeTable 7.Group Timing Relationship and Tolerances

Offset

Group3V66 to PCI

Table 8.USB to DOT Phase Offset

ParameterDOT SkewUSB SkewVCH SKew

Typical0°180°0°

Value0.0ns0.0ns0.0ns

Tolerance1000 ps1000 ps1000 ps

Conditions3V66 Leads PCI

Min.1.5ns

Max.3.5ns

Test and Measurement Set-up

Table 9.Maximum Lumped Capacitive Output Loads

ClockPCI Clocks3V66 ClocksUSB ClockDOT ClockREF Clock

Max Load

3030201030

UnitspFpFpFpFpF

For Differential CPU and SRC Output Signals

The following diagram shows lumped test load configurationsfor the differential Host Clock Outputs.

CPUT󰀖󰀖:󰀗󰀜󰀑󰀜:󰀖󰀖:TPCBMeasurementPoint2pFCPUCIREF󰀗󰀚󰀘:TPCB󰀗󰀜󰀑󰀜:MeasurementPoint2pFFigure 7. 0.7V Load Configuration

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CY28405-3Output under TestProbeLoad Cap3.3V signals tDC--3.3V2.0V1.5V0.8V0VTrTfFigure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)

Table 10.CPU Clock Current Select Function

Board Target Trace/Term Z

50 Ohms

Reference R, IREF – VDD (3*RREF)RREF = 475 1%, IREF = 2.32mA

Output Current IOH = 6*IREF

VOH @ Z0.7V @ 50

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CY28405-3Ordering Information

Part Number

CY28405OC-3CY28405OC-3T

Package Type

48-pin SSOP48-pin SSOP – Tape and Reel

Product FlowCommercial, 0q to 70qCCommercial, 0q to 70qC

Package Drawing and Dimensions

48-leadShrunkSmallOutlinePackageO485185061*C

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use innormal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additionalprocessing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change anycircuitry or specification without notice.

Rev1.0,November 22, 2006Page 16 of 16