用VHDL语言设计触发器

D触发器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

ENTITY DFF2 IS

PORT(CLK:IN STD_LOGIC;

D:IN STD_LOGIC;

Clr:IN STD_LOGIC;

Set:IN STD_LOGIC;

Q:OUT STD_LOGIC);

END ENTITY DFF2;

ARCHITECTURE bhv OF DFF2 IS

BEGIN

PROCESS(CLK,Clr,Set)

BEGIN

If set='0'then q<='1';

elsif CLK'EVENT AND CLK ='1'

THEN

if clr='1'then q<='0';

else Q<=D;

end if;

END IF;

END PROCESS;

END ARCHITECTURE bhv;

JK触发器

library IEEE;

use IEEE.std_logic_11.all;

entity JK_FF is

port (Jk: in std_logic_vector (1 downto 0);

Clock, Reset,Clear : in std_logic;

Q, Qbar : out std_logic);

end entity JK_FF;

architecture sig of JK_FF is

signal state : std_logic;

begin

p0: process (Clock, Reset, Clear) is

begin

if Clear = '1' then state <= '0';

elsif Clock'event and clock ='1'

then

if Reset='0' then state <= '1';

else case jk is

when \"11\" =>

state <= not state;

when \"10\" =>

state <= '1';

when \"01\" =>

state <= '0';

when others =>

null;

end case;

end if;

end if;

end process p0;

Q <= state;

Qbar <= not state;

end architecture sig;

（4）RS锁存器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RS_clk IS

PORT( S,R,res :IN std_logic;

Q,NOT_Q:out std_logic);

END RS_clk;

ARCHITECTURE behav OF RS_clk IS

signal sel1,sel2: std_logic;

BEGIN

process(res,sel1,sel2)

begin

if res='0'

then

sel1<='0';

sel2<='1';

elsif (S='1' and R='0')

then sel1<='1'; sel2<='0';

elsif (S='0' and R='1')

then

sel1<='0';

sel2<='1';

elsif (S='0' and R='0')

then

sel1<=sel1; sel2<=sel2;

end if;

Q<=sel1;NOT_Q<=sel2;

end process;

END behav;