Method and device for testing memory circuits

专利名称：Method and device for testing memory

circuits

发明人：Haukness, Brent S.申请号：EP97119055.8申请日：19971031公开号：EP0840328A2公开日：19980506

专利附图：

摘要：An integrated circuit memory device (10) has a current-mode data compressiontest mode. The memory device (10) includes a memory array having a plurality of sub-arrays (12) of memory cells. The memory cells are selected for read operations by Y-

select lines (18) and word lines (16). Selected memory cells are coupled to main amplifiercircuits (28) via bit lines (14), sense amplifiers (20), sub-input/output lines (22), sub-amplifier circuits (24), and main input/output lines (26). Each main amplifier circuit (28) isoperable, during a normal read operation, to provide a data output (DOUT) representinga data state of a selected memory cell. During a test mode read operation, each mainamplifier circuit (28) is operable to provide a data output (DOUT) representing a datastate of a plurality of selected memory cells if the plurality of selected memory cellshave the same data state, and to provide an error signal (ERROR) if the plurality ofselected memory cells have different data states. The test mode read operation ischaracterized by activating a Y-select line (18) and a plurality of word lines (16) to select aplurality of memory cells that are coupled to different sub-amplifier circuits (24) thatfeed the same main amplifier circuit (28).

申请人：TEXAS INSTRUMENTS INCORPORATED

地址：13500 North Central Expressway Dallas Texas 75265 US

国籍：US

代理机构：Schwepfinger, Karl-Heinz, Dipl.-Ing.

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