Data-processing apparatus including a cache memory

专利名称：Data-processing apparatus including a cache

memory

发明人：Cole, Terence Michael,Poskitt, Geoffrey申请号：EP89307983.0申请日：19890804公开号：EP0365117A3公开日：19910320

专利附图：

摘要：A data processing unit accesses data in a cache, by means of a virtual address, Ifthe data is not in the cache, the virtual address is translated, by means of a memorymanagement unit (MMU), into a physical address for accessing the main memory. The

MMU can also access the cache, by means of a physical address, to retrieve page tableentries held in the cache. This avoids the need for a main memory access to retrieve thepage table entries, and hence speeds up the address translation operation. Thephysically addressed entries in the cache are tagged with a reserved context number todistinguish them from the virtually addressed data.

申请人：INTERNATIONAL COMPUTERS LIMITED

地址：ICL House Putney, London, SW15 1SW GB

国籍：GB

代理机构：Guyatt, Derek Charles

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