Clock generating circuit

专利名称：Clock generating circuit发明人：Win Chaivipas,Atsushi Matsuda申请号：US14070005申请日：20131101公开号：US088102B2公开日：20141007

专利附图：

摘要：A clock generating circuit includes: a counter that counts a number of pulses ofan oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delayingthe oscillation clock signal; a second time-to-digital converter that generates a plurality

of phases of second clock signals by delaying the oscillation clock signal by a short delaytime; a third time-to-digital converter that generates a plurality of phases of third clocksignals by delaying the delayed first clock signal; a delay control unit that outputs adelay control signal based on a difference between a cycle of the oscillation clock signaland a target cycle; and an oscillator that generates, based on a cycle of the referenceclock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the referenceclock signal.

申请人：Fujitsu Limited

地址：Kawasaki JP

国籍：JP

代理机构：Fujitsu Patent Center

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