MX29F400CT-B

•524,288 x 8/262,144 x 16 switchable•Single power supply operation

- 5.0V only operation for read, erase and programoperation

•Fast access time: 55/70/90ns

•Compatible with MX29F400T/B device•Low power consumption

- 40mA maximum active current(5MHz)- 1uA typical standby current•Command register architecture

- Byte/word Programming (9us/11us typical)

- Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and K-Byte x7)

•Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors withErase Suspend capability.

- Automatically program and verify data at specifiedaddress

•Erase suspend/Erase Resume

- Suspends an erase operation to read data from, orprogram data to, another sector that is not beingerased, then resumes the erase•Status Reply

- Data# Polling & Toggle bit for detection of programand erase cycle completion

•Ready/Busy pin (RY/BY#)

- Provides a hardware method of detecting program orerase cycle completion

•Sector protect/chip unprotect for 5V only system•Sector protection

- Hardware method to disable any combination ofsectors from program or erase operations

- Temporary sector unprotect allows code changes inpreviously locked sectors

•100,000 minimum erase/program cycles

•Latch-up protected to 100mA from -1V to VCC+1V•Boot Code Sector Architecture- T = Top Boot Sector- B = Bottom Boot Sector

•Low VCC write inhibit is equal to or less than 3.2V•Package type:- 44-pin SOP- 48-pin TSOP

- All Pb-free devices are RoHS Compliant•Compatibility with JEDEC standard

- Pinout and software compatible with single-powersupply Flash

•20 years data retention

GENERAL DESCRIPTION

The MX29F400C T/B is a 4-mega bit Flash memory or-ganized as 512K bytes of 8 bits or 256K words of 16 bits.MXIC's Flash memories offer the most cost-effective andreliable read/write non-volatile random access memory.The MX29F400C T/B is packaged in 44-pin SOP, 48-pinTSOP. It is designed to be reprogrammed and erased insystem or in standard EPROM programmers.

The standard MX29F400C T/B offers access time asfast as 55ns, allowing operation of high-speed micropro-cessors without wait states. To eliminate bus conten-tion, the MX29F400C T/B has separate chip enable (CE#)and output enable (OE#) controls.

MXIC's Flash memories augment EPROM functionalitywith in-circuit electrical erasure and programming. TheMX29F400C T/B uses a command register to managethis functionality. The command register allows for 100%TTL level control inputs and fixed power supply levels

P/N:PM1200

during erase and programming, while maintaining maxi-mum EPROM compatibility.

MXIC Flash technology reliably stores memory contentseven after 100,000 erase and program cycles. The MXICcell is designed to optimize the erase and programmingmechanisms. In addition, the combination of advancedtunnel oxide processing and low internal electric fieldsfor erase and program operations produces reliable cy-cling. The MX29F400C T/B uses a 5.0V±10% VCC sup-ply to perform the High Reliability Erase and auto Pro-gram/Erase algorithms.

The highest degree of latch-up protection is achievedwith MXIC's proprietary non-epi process. Latch-up pro-tection is proved for stresses up to 100 milliamps onaddress and data pin from -1V to VCC + 1V.

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MX29F400C T/BPIN CONFIGURATIONS44 SOP(500 mil)

NCRY/BY#A17A7A6A5A4A3A2A1A0CE#GNDOE#Q0Q8Q1Q9Q2Q10Q3Q112345671011121314151617181920212244434241403938373635343332313029282726252423RESET#WE#A8A9A10A11A12A13A14A15A16BYTE#GNDQ15/A-1Q7Q14Q6Q13Q5Q12Q4VCCPIN DESCRIPTION

SYMBOLPIN NAMEA0~A17Q0~Q14Q15/A-1CE#WE#BYTE#RESET#OE#RY/BY#VCCGND

Address InputData Input/Output

Q15(Word mode)/LSB addr(Byte mode)Chip Enable InputWrite Enable InputWord/Byte Selection inputHardware Reset Pin/Sector ProtectUnlock

Output Enable InputReady/Busy OutputPower Supply Pin (+5V)Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

A15A14A13A12A11A10A9A8NCNCWE#RESET#NCNCRY/BY#NCA17A7A6A5A4A3A2A1123456710111213141516171819202122232448474443424140393837363534333231302928272625A16BYTE#GNDQ15/A-1Q7Q14Q6Q13Q5Q12Q4VCCQ11Q3Q10Q2Q9Q1Q8Q0OE#GNDCE#A0MX29F400CT/CBMX29F400CT/CBP/N:PM1200REV. 1.0, DEC. 20, 2005

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MX29F400C T/BSECTOR STRUCTURE

MX29F400CT TOP BOOT SECTOR ADDRESS TABLE

Sector Size(Kbytes/Kwords)/32/32/32/32/32/32/3232/168/48/416/8

Address Range (in hexadecimal)(x8)(x16)Address RangeAddress Range00000h-0FFFFh10000h-1FFFFh20000h-2FFFFh30000h-3FFFFh40000h-4FFFFh50000h-5FFFFh60000h-6FFFFh70000h-77FFFh78000h-79FFFh7A000h-7BFFFh7C000h-7FFFFh

00000h-07FFFh08000h-0FFFFh10000h-17FFFh18000h-1FFFFh20000h-27FFFh28000h-2FFFFh30000h-37FFFh38000h-3BFFFh3C000h-3CFFFh3D000h-3DFFFh3E000h-3FFFFh

SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10

A1700001111111

A1600110011111

A1501010101111

A14XXXXXXX0111

A13XXXXXXXX001

A12XXXXXXXX01X

MX29F400CB BOTTOM BOOT SECTOR ADDRESS TABLE

Sector Size(Kbytes/Kwords)16/88/48/432/16/32/32/32/32/32/32/32

Address Range (in hexadecimal)(x8)(x16)Address RangeAddress Range00000h-03FFFh04000h-05FFFh06000h-07FFFh08000h-0FFFFh10000h-1FFFFh20000h-2FFFFh30000h-3FFFFh40000h-4FFFFh50000h-5FFFFh60000h-6FFFFh70000h-7FFFFh

00000h-01FFFh02000h-02FFFh03000h-03FFFh04000h-07FFFh08000h-0FFFFh10000h-17FFFh18000h-1FFFFh20000h-27FFFh28000h-2FFFFh30000h-37FFFh38000h-3FFFFh

SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10

A1700000001111

A1600000110011

A1500001010101

A140001XXXXXXX

A13011XXXXXXXX

A12X01XXXXXXXX

Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode.

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MX29F400C T/BBLOCK DIAGRAM

CE#OE#WE#CONTROLINPUTLOGICPROGRAM/ERASEHIGH VOLTAGEWRITESTATEMACHINE(WSM)STATEREGISTERX-DECODERADDRESSLATCHA0-A17ANDBUFFERFLASHARRAYARRAYSOURCEHVCOMMANDDATADECODERY-DECODERY-PASS GATESENSEAMPLIFIERPGMDATAHVCOMMANDDATA LATCHPROGRAMDATA LATCHQ0-Q15/A-1I/O BUFFERP/N:PM1200REV. 1.0, DEC. 20, 2005

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MX29F400C T/BAUTOMATIC PROGRAMMING

The MX29F400C T/B is byte programmable using theAutomatic Programming algorithm. The Automatic Pro-gramming algorithm makes the external system do notneed to have time out sequence nor to verify the dataprogrammed. The typical chip programming time at roomtemperature of the MX29F400C T/B is less than 4.5 sec-onds.

dard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Thenthe device automatically times the erase pulse width,provides the erase verification, and counts the numberof sequences. A status bit toggling between consecu-tive read cycles provides feedback to the user as to thestatus of the programming operation.

Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle,addresses are latched on the falling edge, and data arelatched on the rising edge of WE# or CE#, whicheverhappens first .

MXIC's Flash technology combines years of EPROMexperience to produce the highest levels of quality, reli-ability, and cost effectiveness. The MX29F400C T/B elec-trically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by us-ing the EPROM programming mechanism of hot electroninjection.

During a program cycle, the state-machine will controlthe program sequences and command register will notrespond to any command set. During a Sector Erasecycle, the command register will only respond to EraseSuspend command. After Erase Suspend is completed,the device stays in read mode. After the state machinehas completed its task, it will allow the command regis-ter to respond to its full command set.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulsesaccording to MXIC's Automatic Chip Erase algorithm.Typical erasure at room temperature is accomplished inless than 4 second. The Automatic Erase algorithm au-tomatically programs the entire array prior to electricalerase. The timing and verification of electrical erase arecontrolled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F400C T/B is sector(s) erasable using MXIC'sAuto Sector Erase algorithm. Sector erase modes allowsectors of the array to be erased in one erase cycle. TheAutomatic Sector Erase algorithm automatically programsthe specified sector(s) prior to electrical erase. The tim-ing and verification of electrical erase are controlled in-ternally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires theuser to only write program set-up commands (including 2unlock write cycle and A0H) and a program command(program data and address). The device automaticallytimes the programming pulse width, provides the pro-gram verification, and counts the number of sequences.A status bit similar to Data# Polling and a status bit tog-gling between consecutive read cycles, provide feedbackto the user as to the status of the programming opera-tion.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user towrite commands to the command register using stan-P/N:PM1200

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MX29F400C T/BTABLE 1. SOFTWARE COMMAND DEFINITIONS

Command

Bus

First BusCycle

Second BusThird BusCycleCycle

Data

Fourth Bus

CycleAddrData

Fifth BusCycleAddr

Sixth BusCycle

Data

CycleAddr

ResetReadRead SiliconID

Sector ProtectVerify

Byte

4

WordByteWord

11444

DataAddrDataAddr DataAddr

XXXHF0HRA

RD

2AAH55H555H55H2AAH55H

555H90HAAAH90H555H90H

ADIADI(SA)

DDIDDIXX00H

555HAAHAAAHAAH555HAAH

x02HXX01H

AAAHAAH

555H55H

AAAH90H

(SA)

00H

x04H01H

Program

WordByte

Chip Erase

WordByte

Sector Erase

WordByte

Sector Erase SuspendSector Erase ResumeUnlock for sectorprotect/unprotect

Note:

1.ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code, A2~A17=do not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH (x8) and 2223H/22ABH (x16) for device code.X = X can be VIL or VIH

RA=Address of memory location to be read.RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.SA = Address to the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and SectorAddress (SA). Write Sequence may be initiated with A11~A17 in either state.

4.For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it

means the sector is still not being protected.

446666116

555HAAHAAAHAAH555HAAHAAAHAAH555HAAHAAAHAAHXXXHB0HXXXH30H555HAAH

2AAH55H

555H80H

555HAAH

2AAH55H

555H20H

2AAH55H555H55H2AAH55H555H55H2AAH55H555H55H

555HA0HAAAHA0H555H80HAAAH80H555H80HAAAH80H

PAPA

PDPD

2AAH55H555H55H2AAH55H555H55H

555H10HAAAH10HSASA

30H30H

555HAAHAAAHAAH555HAAHAAAHAAH

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MX29F400C T/BCOMMAND DEFINITIONS

Device operations are selected by writing specific addressand data sequences into the command register. Writingincorrect address and data values or writing them in theimproper sequence will reset the device to the read mode.Table 1 defines the valid register command sequences.

Note that the Erase Suspend (B0H) and Erase Resume(30H) commands are valid only while the Sector Eraseoperation is in progress. Either of the two reset com-mand sequences will reset the device(when applicable).

TABLE 2. MX29F400C T/B BUS OPERATION

Pins

Mode

Read Silicon ID

Manufacture Code(1)Read Silicon IDDevice Code(1)ReadStandby

Output DisableWrite

Sector Protect without 12Vsystem (6)

Chip Unprotect without 12Vsystem (6)

Verify Sector Protect/Unprotectwithout 12V system (7)Reset

CE#LLLHLLLLLX

OE#LLLXHHHHLX

WE#HHHXHLLLHX

A0LHA0XXA0XXXX

A1LLA1XXA1XXHX

A6XXA6XXA6LHXX

A9VID(2)VID(2)A9XXA9HHHX

Q0 ~ Q15

C2H (Byte mode)00C2H (Word mode)23H/ABH (Byte mode)2223H/22ABH (Word mode)DOUT

HIGH ZHIGH ZDIN(3)XXCode(5)HIGH Z

NOTES:

1.Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.2.VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.3.Refer to Table 1 for valid Data-In during a write operation.4.X can be VIL or VIH.

5.Code=00H/XX00H means unprotected.Code=01H/XX01H means protected.

A17~A12=Sector address for sector protect.

6.Refer to sector protect/unprotect algorithm and waveform.

Must issue \"unlock for sector protect/unprotect\" command before \"sector protect/unprotect without 12V system\"command.

7.The \"verify sector protect/unprotect without 12V system\" is only following \"Sector protect/unprotect without 12Vsystem\" command.

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MX29F400C T/BREAD/RESET COMMAND

The read or reset operation is initiated by writing theread/reset command sequence into the command reg-ister. Microprocessor read cycles retrieve array data.The device remains enabled for reads until the commandregister contents are altered.

If program-fail or erase-fail happen, the write of F0H willreset the device to abort the operation. A valid com-mand must then be written to place the device in thedesired state.

SET-UP AUTOMATIC CHIP/SECTOR ERASECOMMANDS

Chip erase is a six-bus cycle operation. There are two\"unlock\" write cycles. These are followed by writing the\"set-up\" command 80H. Two more \"unlock\" write cy-cles are then followed by the chip erase command 10H.The Automatic Chip Erase does not require the deviceto be entirely pre-programmed prior to executing the Au-tomatic Chip Erase. Upon executing the Automatic ChipErase, the device will automatically program and verifythe entire memory for an all-zero data pattern. When thedevice is automatically verified to contain an all-zeropattern, a self-timed chip erase and verify begin. Theerase and verify operations are completed when the dataon Q7 is \"1\" at which time the device returns to theRead mode. The system is not required to provide anycontrol or timing during these operations.

When using the Automatic Chip Erase algorithm, notethat the erase automatically terminates when adequateerase margin has been achieved for the memory array(noerase verification command is required).

If the Erase operation was unsuccessful, the data onQ5 is \"1\"(see Table 4), indicating the erase operationexceed internal timing limit.

The automatic erase begins on the rising edge of thelast WE# or CE#, whichever happens later, pulse in thecommand sequence and terminates when the data onQ7 is \"1\" and the data on Q6 stops toggling for two con-secutive read cycles, at which time the device returnsto the Read mode.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications wherethe local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while thedevice resides in the target system. PROM program-mers typically access signature codes by raising A9 toa high voltage. However, multiplexing high voltage ontoaddress lines is not generally desired system designpractice.

The MX29F400C T/B contains a Silicon-ID-Read opera-tion to supplement traditional PROM programming meth-odology. The operation is initiated by writing the readsilicon ID command sequence into the command regis-ter. Following the command write, a read cycle withA1=VIL,A0=VIL retrieves the manufacturer code of C2H/00C2H. A read cycle with A1=VIL, A0=VIH returns thedevice code of 23H/2223H for MX29F400CT, ABH/22ABHfor MX29F400CB.

TABLE 3. EXPANDED SILICON ID CODE

Pins

Manufacture codeDevice codefor MX29F400CTDevice codefor MX29F400CBSector ProtectionVerification

WordByteWordByteWordByte

A0VILVILVIHVIHVIHVIHXX

A1VILVILVILVILVILVILVIHVIH

Q15~Q8Q700HX22HX22HXXX

11001100

Q611000000

Q500111100

Q400000000

Q300001100

Q2Q100000000

11111100

Q000111110

Code(Hex)00C2HC2H2223H23H22ABHABH

01H (Protected)00H (Unprotected)

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MX29F400C T/BSECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-vice to be entirely pre-programmed prior to executingthe Automatic Set-up Sector Erase command and Auto-matic Sector Erase command. Upon executing the Au-tomatic Sector Erase command, the device will auto-matically program and verify the sector(s) memory foran all-zero data pattern. The system is not required toprovide any control or timing during these operations.When the sector(s) is automatically verified to containan all-zero pattern, a self-timed sector erase and verifybegin. The erase and verify operations are completewhen the data on Q7 is \"1\" and the data on Q6 stopstoggling for two consecutive read cycles, at which timethe device returns to the Read mode. The system is notrequired to provide any control or timing during theseoperations.

When using the Automatic Sector Erase algorithm, notethat the erase automatically terminates when adequate

erase margin has been achieved for the memory array(no erase verification command is required). Sectorerase is a six-bus cycle operation. There are two \"un-lock\" write cycles. These are followed by writing the set-up command 80H. Two more \"unlock\" write cycles arethen followed by the sector erase command 30H. Thesector address is latched on the falling edge of WE# orCE#, whichever happens later, while the command(data)is latched on the rising edge of WE# or CE#, whicheverhappens first. Sector addresses selected are loadedinto internal register on the sixth falling edge of WE# orCE#, whichever happens later. Each successive sectorload cycle started by the falling edge of WE# or CE#,whichever happens later, must begin within 30us fromthe rising edge of the preceding WE# or CE#, whicheverhappens First, otherwise, the loading period ends andinternal auto sector erase cycle starts. (Monitor Q3 todetermine if the sector erase timer window is still open,see section Q3, Sector Erase Timer.) Any command otherthan Sector Erase(30H) or Erase Suspend(B0H) duringthe time-out period resets the device to read mode.

Table 4. Write Operation Status

Status

Byte Program in Auto Program AlgorithmAuto Erase Algorithm

Erase Suspend Read

(Erase Suspended Sector)

Erase Suspended Mode

Q7Note1Q7#01

Q6ToggleToggleNoToggleDataToggleToggleToggleToggle

Q5Note2000

Q3N/A1

Q2RY/BY#NoToggleToggle

00110000

N/AToggle

In Progress

Erase Suspend ReadData(Non-Erase Suspended Sector)Erase Suspend Program

Q7#Q7#0Q7#

DataDataData0111

N/AN/A1N/A

N/ANoToggleToggleN/A

Byte Program in Auto Program Algorithm

Exceeded

Time Limits Auto Erase Algorithm

Erase Suspend Program

Note:

1.Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.2.Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See \"Q5:Exceeded Timing Limits \" for more information.

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MX29F400C T/BERASE SUSPEND

This command only has meaning while the state ma-chine is executing Automatic Sector Erase operation, andtherefore will only be responded during Automatic SectorErase operation. When the Erase Suspend command iswritten during a sector erase operation, the device re-quires a maximum of 20us to suspend the erase opera-tions. However, When the Erase Suspend command iswritten during the sector erase time-out, the device im-mediately terminates the time-out period and suspendsthe erase operation. After this command has been ex-ecuted, the command register will initiate erase suspendmode. The state machine will return to read mode auto-matically after suspend is ready. At this time, state ma-chine only allows the command register to respond tothe Read Memory Array, Erase Resume and programcommands.

The system can determine the status of the programoperation using the Q7 or Q6 status bits, just as in thestandard program operation. After an erase-suspend pro-gram operation is complete, the system can once againread array data within non-suspended sectors.

next WE# or CE#, pulse causes a transition to an activeprogramming operation. Addresses are latched on thefalling edge, and data are internally latched on therising edge of the WE# or CE#, whichever happens first,pulse. The rising edge of WE# or CE#, whichever hap-pens first, also begins the programming operation. Thesystem is not required to provide further controls or tim-ings. The device will automatically provide an adequateinternally generated program pulse and verify margin.If the program operation was unsuccessful, the data onQ5 is \"1\"(see Table 4), indicating the program operationexceed internal timing limit. The automatic programmingoperation is completed when the data read on Q6 stopstoggling for two consecutive read cycles and the dataon Q7 and Q6 are equivalent to data written to these twobits, at which time the device returns to the Read mode(noprogram verify command is required).

DATA# POLLING-Q7

The MX29F400C T/B also features Data# Polling as amethod to indicate to the host system that the Auto-matic Program or Erase algorithms are either in progressor completed.

While the Automatic Programming algorithm is in opera-tion, an attempt to read the device will produce thecomplement data of the data last written to Q7. Uponcompletion of the Automatic Program Algorithm an at-tempt to read the device will produce the true data lastwritten to Q7. The Data# Polling feature is valid after therising edge of the fourth WE# or CE#, whichever hap-pens first, pulse of the four write pulse sequences forautomatic program.

While the Automatic Erase algorithm is in operation, Q7will read \"0\" until the erase operation is competed. Uponcompletion of the erase operation, the data on Q7 willread \"1\". The Data# Polling feature is valid after therising edge of the sixth WE# or CE#, whichever happensfirst pulse of six write pulse sequences for automaticchip/sector erase.

The Data# Polling feature is active during Automatic Pro-gram/Erase algorithm or sector erase time-out. (see sec-tion Q3 Sector Erase Timer)

ERASE RESUME

This command will cause the command register to clearthe suspend state and return back to Sector Erase modebut only if an Erase Suspend command was previouslyissued. Erase Resume will not have any effect in allother conditions. Another Erase Suspend command canbe written after the chip has resumed erasing. However,a 400us time delay must be required after the erase re-sume command, if the system implements an endlesserase suspend/resume loop, or the number of erase sus-pend/resume is exceeded 1024 times. The erase timeswill be expended if the erase behavior always be sus-pended.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle com-mand sequence is required. There are two \"unlock\" writecycles. These are followed by writing the Automatic Pro-gram command A0H.

Once the Automatic Program command is initiated, the

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MX29F400C T/BRY/BY#:Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin thatindicates whether an Automatic Erase/Program algorithmis in progress or complete. The RY/BY# status is validafter the rising edge of the final WE# or CE#, whicheverhappens first, pulse in the command sequence. SinceRY/BY# is an open-drain output, several RY/BY# pinscan be tied together in parallel with a pull-up resistor toVcc.

If the output is low (Busy), the device is actively erasingor programming. (This includes programming in the EraseSuspend mode.) If the output is high (Ready), the deviceis ready to read array data (including during the EraseSuspend mode), or is in the standby mode.Table 4 shows the outputs for RY/BY#.

pended. Alternatively, the system can use Q7.If a program address falls within a protected sector, Q6toggles for approximately 2 us after the program com-mand sequence is written, then returns to reading arraydata.

Q6 also toggles during the erase-suspend-program mode,and stops toggling once the Automatic Program algorithmis complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The \"Toggle Bit II\" on Q2, when used with Q6, indicateswhether a particular sector is actively erasing (that is,the Automatic Erase algorithm is in process), or whetherthat sector is erase-suspended. Toggle Bit I is valid afterthe rising edge of the final WE# or CE#, whichever hap-pens first, pulse in the command sequence.

Q2 toggles when the system reads at addresses withinthose sectors that have been selected for erasure. (Thesystem may use either OE# or CE# to control the readcycles.) But Q2 cannot distinguish whether the sectoris actively erasing or is erase-suspended. Q6, by com-parison, indicates whether the device is actively eras-ing, or is in Erase Suspend, but cannot distinguish whichsectors are selected for erasure. Thus, both status bitsare required for sectors and mode information. Refer toTable 4 to compare outputs for Q2 and Q6.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-gram or Erase algorithm is in progress or complete, orwhether the device has entered the Erase Suspend mode.Toggle Bit I may be read at any address, and is validafter the rising edge of the final WE# or CE#, whicheverhappens first, pulse in the command sequence (prior tothe program or erase operation), and during the sectortime-out.

During an Automatic Program or Erase algorithm opera-tion, successive read cycles to any address cause Q6to toggle. The system may use either OE# or CE# tocontrol the read cycles. When the operation is complete,Q6 stops toggling.

After an erase command sequence is written, if all sec-tors selected for erasing are protected, Q6 toggles andreturns to reading array data. If not all selected sectorsare protected, the Automatic Erase algorithm erases theunprotected sectors, and ignores the selected sectorsthat are protected.

The system can use Q6 and Q2 together to determinewhether a sector is actively erasing or is erase sus-pended. When the device is actively erasing (that is, theAutomatic Erase algorithm is in progress), Q6 toggling.When the device enters the Erase Suspend mode, Q6stops toggling. However, the system must also use Q2to determine which sectors are erasing or erase-sus-

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bitstatus, it must read Q7-Q0 at least twice in a row todetermine whether a toggle bit is toggling. Typically, thesystem would note and store the value of the toggle bitafter the first read. After the second read, the systemwould compare the new value of the toggle bit with thefirst. If the toggle bit is not toggling, the device has com-pleted the program or erase operation. The system canread array data on Q7-Q0 on the following read cycle.However, if after the initial two read cycles, the systemdetermines that the toggle bit is still toggling, the sys-tem also should note whether the value of Q5 is high(see the section on Q5). If it is, the system should then

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11

MX29F400C T/Bdetermine again whether the toggle bit is toggling, sincethe toggle bit may have stopped toggling just as Q5 wenthigh. If the toggle bit is no longer toggling, the devicehas successfully completed the program or erase opera-tion. If it is still toggling, the device did not complete theoperation successfully, and the system must write thereset command to return to reading array data.The remaining scenario is that system initially determinesthat the toggle bit is toggling and Q5 has not gone high.The system may continue to monitor the toggle bit andQ5 through successive read cycles, determining the sta-tus as described in the previous paragraph. Alternatively,it may choose to perform other system tasks. In thiscase, the system must start at the beginning of the al-gorithm when it returns to determine the status of theoperation.

program a non blank location without erasing. In thiscase the device locks out and never completes the Au-tomatic Algorithm operation. Hence, the system neverreads a valid data on Q7 bit and Q6 never stops toggling.Once the Device has exceeded timing limits, the Q5 bitwill indicate a \"1\". Please note that this is not a devicefailure condition since the device was incorrectly used.

DATA PROTECTION

The MX29F400C T/B is designed to offer protectionagainst accidental erasure or programming caused byspurious system level signals that may exist during powertransition. During power up the device automatically re-sets the state machine in the Read mode. In addition,with its control register architecture, alteration of thememory contents only occurs after successful comple-tion of specific command sequences. The device alsoincorporates several features to prevent inadvertent writecycles resulting from VCC power-up and power-down tran-sition or system noise.

Q5

Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceededthe specified limits (internal pulse count). Under theseconditions Q5 will produce a \"1\". This time-out conditionindicates that the program or erase cycle was not suc-cessfully completed. Data# Polling and Toggle Bit arethe only operating functions of the device under this con-dition.

If this time-out condition occurs during sector erase op-eration, it specifies that a particular sector is bad and itmay not be reused. However, other sectors are still func-tional and may be used for the program or erase opera-tion. The device must be reset to use other sectors.Write the Reset command sequence to the device, andthen execute program or erase command sequence. Thisallows the system to continue to use the other activesectors in the device.

If this time-out condition occurs during the chip eraseoperation, it specifies that the entire chip is bad or com-bination of sectors are bad.

If this time-out condition occurs during the byte program-ming operation, it specifies that the entire sector con-taining that byte is bad and this sector may not be re-used, (other sectors are still functional and can be re-used).

The time-out condition may also appear if a user tries to

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previouslyprotected sector to change data in-system. The Tempo-rary Sector Unprotect mode is activated by setting theRESET# pin to VID(11.5V-12.5V). During this mode, for-merly protected sectors can be programmed or erasedas un-protected sector. Once VID is remove from theRESET# pin, all the previously protected sectors are pro-tected again.

Q3

Sector Erase Timer

After the completion of the initial sector erase commandsequence, the sector erase time-out will begin. Q3 willremain low until the time-out is complete. Data# Pollingand Toggle Bit are valid after the initial sector erase com-mand sequence.

If Data# Polling or the Toggle Bit indicates the device hasbeen written with a valid erase command, Q3 may beused to determine if the sector erase timer window isstill open. If Q3 is high (\"1\") the internally controllederase cycle has begun; attempts to write subsequentcommands to the device will be ignored until the erase

REV. 1.0, DEC. 20, 2005

P/N:PM1200

12

MX29F400C T/Boperation is completed as indicated by Data# Polling orToggle Bit. If Q3 is low (\"0\"), the device will accept addi-tional sector erase commands. To insure the commandhas been accepted, the system software should checkthe status of Q3 prior to and following each subsequentsector erase command. If Q3 were high on the secondstatus check, the command may not have been accepted.

WRITE PULSE \"GLITCH\" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,CE# = VIH or WE# = VIH. To initiate a write cycle CE#and WE# must be a logical zero while OE# is a logicalone.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each deviceshould have a 0.1uF ceramic capacitor connected be-tween its VCC and GND.

P/N:PM1200REV. 1.0, DEC. 20, 2005

13

MX29F400C T/BTEMPORARY SECTOR UNPROTECT OPERATIONStartRESET# = VID (Note 1)Perform Erase or Program OperationOperation CompletedRESET# = VIHTemporary Sector Unprotect Completed(Note 2)Notes : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V2. All previously protected sectors are protected again.P/N:PM1200REV. 1.0, DEC. 20, 2005

14

MX29F400C T/BTEMPORARY SECTOR UNPROTECTParameter Std.DescriptiontVIDRtRSPNote:Not 100% testedVID Rise and Fall Time (See Note)RESET# Setup Time for Temporary Sector UnprotectTest SetupAll Speed OptionsUnitMinMin5004nsusTEMPORARY SECTOR UNPROTECT TIMING DIAGRAM12VRESET#0 or 5VtVIDRProgram or Erase Command Sequence0 or 5VtVIDRCE#WE#tRSPRY/BY#P/N:PM1200REV. 1.0, DEC. 20, 2005

15

MX29F400C T/BAC CHARACTERISTICSParameter StdtREADY1tREADY2tRP1tRP2tRHtRB1tRB2DescriptionRESET# PIN Low (During Automatic Algorithms)to Read or Write (See Note)RESET# PIN Low (NOT During AutomaticAlgorithms) to Read or Write (See Note)RESET# Pulse Width (During Automatic Algorithms)RESET# High Time Before Read(See Note)RY/BY# Recovery Time(to CE#, OE# go low)RY/BY# Recovery Time(to WE# go low)MINMINMINMIN105000050usnsnsnsnsRESET# Pulse Width (NOT During Automatic Algorithms)MINMAX500nsTest SetupAll Speed OptionsUnitMAX20usNote:Not 100% testedRESET# TIMING WAVEFORMRY/BY#CE#, OE#tRHRESET#tRP2tReady2Reset Timing NOT during Automatic AlgorithmstReady1RY/BY#tRB1CE#, OE# WE#tRB2RESET#tRP1Reset Timing during Automatic AlgorithmsP/N:PM1200REV. 1.0, DEC. 20, 2005

16

MX29F400C T/BPOWER-UP SEQUENCE

The MX29F400C T/B powers up in the Read only mode.In addition, the memory contents may only be alteredafter successful completion of the predefined commandsequences.

ABSOLUTE MAXIMUM RATINGS

RATING

Ambient Operating TemperatureAmbient Temperature with PowerApplied

Storage TemperatureApplied Input VoltageApplied Output VoltageVCC to Ground PotentialA9

VALUE

-40oC to 85oC (*)-55oC to 125oC-65oC to 125oC-0.5V to 7.0V-0.5V to 7.0V-0.5V to 7.0V-0.5V to 13.5V

SECTOR PROTECTION WITHOUT 12V SYS-TEM

The MX29F400C T/B also feature a hardware sectorprotection method in a system without 12V power supply.The programming equipment do not need to supply 12volts to protect sectors. The details are shown in sectorprotect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F400C T/B also feature a hardware chipunprotection method in a system without 12V powersupply. The programming equipment do not need tosupply 12 volts to unprotect all sectors. The details areshown in chip unprotect algorithm and waveform.

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXI-MUM RATINGS may cause permanent damage to the de-vice. This is a stress rating only and functional operationalsections of this specification is not implied. Exposure to ab-solute maximum rating conditions for extended period mayaffect reliability.

NOTICE:

Specifications contained within the following tables are sub-ject to change.

* The automotive grade is under development.

P/N:PM1200REV. 1.0, DEC. 20, 2005

17

MX29F400C T/BCAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOLCIN1CIN2COUT

PARAMETERInput CapacitanceControl Pin CapacitanceOutput Capacitance

MIN.

TYP

MAX.81212

UNITpFpFpF

CONDITIONSVIN = 0VVIN = 0VVOUT = 0V

READ OPERATION

DC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ±10%

SYMBOLPARAMETERILIILOISB1ISB2ICC1ICC2VILVIHVOLVOH1VOH2

Input Low Voltage

Input High Voltage(NOTE 2)Output Low VoltageOutput High Voltage(TTL)

2.4

Output High Voltage(CMOS)VCC-0.4

-0.3(NOTE 1)0.7xVCC

Operating VCC currentInput Leakage CurrentOutput Leakage CurrentStandby VCC current

MIN.

TYP

MAX.1101

1(Note3)5(Note3)

40500.8VCC + 0.30.45

UNITuAuAmAuAmAmAVVVVV

IOL = 2.1mA, VCC= VCC MINIOH = -2mA, VCC= VCC MINIOH = -100uA,VCC=VCC MINCONDITIONSVIN = GND to VCCVOUT = GND to VCCCE# = VIHCE# = VCC ± 0.3VIOUT = 0mA, f=5MHzIOUT= 0mA, f=10MHz

NOTES:

1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.3.ISB2 20uA max. for Automotive grade. Which is under development.

P/N:PM1200REV. 1.0, DEC. 20, 2005

18

MX29F400C T/BAC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ± 10%

29F400C-5529F400C-7029F400C-90SYMBOLPARAMETERtACCtCEtOEtDFtOH

Address to Output DelayCE# to Output DelayOE# to Output DelayOE# High to Output Float(Note 1)

Address to Output hold

MIN.MAX.MIN.555530

MAX.707030

MIN. MAX.

909035

00

20

UNITnsnsnsnsns

ConditionsCE#=OE#=VILOE#=VILCE#=VILCE#=VILCE#=OE#=VIL

00

2000

20

TEST CONDITIONS:

•Input pulse levels: 0.45V/0.7xVCC for 70ns & 90ns,0V/0.7xVCC for 55ns

•Input rise and fall times: is equal to or less than 10nsfor 70ns & 90ns, 5ns for 55ns

•Output load: 1 TTL gate + 100pF (Including scope andjig) for 70ns & 90ns, 1TTLgate+30pF for 55ns max.•Reference levels for measuring timing: 0.8V, 2.0V for70ns & 90ns,1.5V for 55ns

Notes:

1.tDF is defined as the time at which the output achievesthe open circuit condition and data is no longer driven.2.Automotive grade is under development.

P/N:PM1200REV. 1.0, DEC. 20, 2005

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MX29F400C T/BREAD TIMING WAVEFORMSVIHAddressesVILADD ValidtCECE#VIHVILWE#VIHVILtOEtDFOE#VIHVILtACCtOHOutputsVOHVOLHIGH ZDATA ValidHIGH ZCOMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATIONDC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ± 10%SYMBOLPARAMETERICC1 (Read)Operating VCC CurrentICC2ICC3 (Program)ICC4 (Erase)ICCESVCC Erase Suspend CurrentMIN.TYPMAX.405050502UNITmAmAmAmAmACONDITIONSIOUT=0mA, f=5MHzIOUT=0mA, f=10MHzIn ProgrammingIn EraseCE#=VIH, Erase SuspendedNotes:1.VIL min. = -0.6V for pulse width is equal to or less than 20ns.2.If VIH is over the specified maximum value, programming operation cannot be guaranteed.3.ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw isthe sum of ICCES and ICC1 or ICC2.4.All current are in RMS unless otherwise noted.5.The Automotive grade is under development.P/N:PM1200REV. 1.0, DEC. 20, 2005

20

MX29F400C T/BAC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ± 10%

Speed Option

SYMBOLtOEStCWCtCEPtCEPHtAStAHtDStDHtCESCtDFtAETCtAETBtAVTtBALtCHtCS

PARAMETEROE# setup time

Command programming cycleWE# programming pulse widthWE# programming pulse width HighAddress setup timeAddress hold timeData setup timeData hold time

CE# setup time before command writeOutput disable time (Note 1)Erase time in auto chip eraseErase time in auto sector eraseProgramming time in auto verify(byte/ word program time)Sector address load timeCE# Hold Time

CE# setup to WE# going low

MIN.MIN.MIN.MIN.MIN.MIN.MIN.MIN.MIN.MAX.TYP.MAX.TYP.MAX.TYP.MAX.MIN.MIN.MIN.

55(Note 2)

05535200453000204320.7159/11300/3605000

7007035200453000204320.7159/11300/3605000

90090452004500204320.7159/11300/3605000

UNITnsnsnsnsnsnsnsnsnsnsssssusususnsns

Notes:

1.tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.2. Under condition of VCC=5V±10%,CL=30pF,VIH/VIL=0.7xVCC/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA.

P/N:PM1200REV. 1.0, DEC. 20, 2005

21

MX29F400C T/BSWITCHING TEST CIRCUITSDEVICE UNDER TEST2.7K ohm+5VCL6.2K ohmDIODES=IN30OR EQUIVALENTCL=100pF Including jig capacitance for 70ns and 90nsCL=30pF Including jig capacitance for 55nsSWITCHING TEST WAVEFORMS for 29F400C T/B-70 and 29F400C T/B-900.7xVCC2.0V2.0VTEST POINTS0.8V0.45V0.8VOUTPUTINPUTAC TESTING: Inputs are driven at 0.7xVCC for a logic \"1\" and 0.45V for a logic \"0\".Input pulse rise and fall times are < 10ns.SWITCHING TEST WAVEFORMS for 29F400C T/B-550.7xVCC1.5VTEST POINTS1.5V0VINPUTOUTPUTAC TESTING: Inputs are driven at 0.7xVCC for a logic \"1\" and 0V for a logic \"0\".Input pulse rise and fall times are < 5ns.P/N:PM1200REV. 1.0, DEC. 20, 2005

22

MX29F400C T/BCOMMAND WRITE TIMING WAVEFORMVCC5VAddressesVIHVILtASADD ValidtAHWE#VIHVILtOEStCEPtCWCtCEPH1CE#VIHVILtCStCHOE#VIHVILVIHVILtDStDHDataDINP/N:PM1200REV. 1.0, DEC. 20, 2005

23

MX29F400C T/BAUTOMATIC PROGRAMMING TIMING WAVEFORMOne byte data is programmed. Verify in fast algorithmand additional programming by external control are notrequired because these operations are executed auto-matically by internal control circuit. Programming comple-tion can be verified by Data# Polling and toggle bit check-ing after automatic verification starts. Device outputsDATA# during programming and DATA# after programmingon Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling,timing waveform)AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)Vcc 5VA11~A17ADD ValidA0~A10WE#555H2AAH555HADD ValidtAStAHtCWCtCEPHtAVTtCESCCE#tCEPOE#Q0,Q1,Q2Q4(Note 1)Q7Command InCommand #AAH(Q0~Q7)Command InCommand #55HCommand InCommand #A0HData IntDStDHCommand InCommand InCommand InData InDATAtDFData# PollingDATA#DATAtOENote :(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bitP/N:PM1200REV. 1.0, DEC. 20, 2005

24

MX29F400C T/BAUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)STARTWrite Data AAH Address 555HWrite Data 55H Address 2AAHWrite Data A0H Address 555HWrite Program Data/AddressToggle Bit CheckingQ6 not ToggledYESNOInvalidCommandNOVerify Word OkYESNOAuto Program CompletedQ5 = 1YESReset.Auto Program ExceedTiming LimitP/N:PM1200REV. 1.0, DEC. 20, 2005

25

MX29F400C T/BAUTOMATIC CHIP ERASE TIMING WAVEFORMAll data in chip are erased. External erase verification isnot required because data is erased automatically byinternal control circuit. Erasure completion can be veri-fied by Data# Polling and toggle bit checking after auto-matic erase starts. Device outputs 0 during erasureand 1 after erasure on Q7.(Q6 is for toggle bit; see togglebit, Data# Polling, timing waveform)AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)Vcc 5VA11~A17A0~A10WE#555H2AAH555H555H2AAH555HtAStAHtCWCtCEPHtAETCCE#tCEPOE#Q0,Q1,Q4(Note 1)Q7Command InCommand #AAHCommand InCommand #55HCommand InCommand #80HCommand InCommand #AAHCommand InCommand #55HCommand InCommand #10HtDStDHCommand InCommand InCommand InCommand InCommand InCommand InData# Polling(Q0~Q7)Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bitP/N:PM1200REV. 1.0, DEC. 20, 2005

26

MX29F400C T/BAUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)STARTWrite Data AAH Address 555HWrite Data 55H Address 2AAHWrite Data 80H Address 555HWrite Data AAH Address 555HWrite Data 55H Address 2AAHWrite Data 10H Address 555HToggle Bit CheckingQ6 not ToggledYESNOInvalidCommandNODATA# PollingQ7 = 1YESNOAuto Chip Erase CompletedQ5 = 1YESResetAuto Chip Erase ExceedTiming LimitP/N:PM1200REV. 1.0, DEC. 20, 2005

27

MX29F400C T/BAUTOMATIC SECTOR ERASE TIMING WAVEFORMSector data indicated by A12 to A17 are erased. Exter-nal erase verify is not required because data are erasedautomatically by internal control circuit. Erasure comple-tion can be verified by Data# Polling and toggle bit check-ing after automatic erase starts. Device outputs 0 dur-ing erasure and 1 after erasure on Q7.(Q6 is for togglebit; see toggle bit, Data# Polling, timing waveform)AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)VCC 5VA12~A17SectorAddress0SectorAddress1SectorAddressnA0~A10555HtAStAH2AAH555H555H2AAHtCWCWE#tCEPHtBALtAETBCE#tCEPOE#tDStDHQ0,Q1,Q4(Note 1)Command InCommand InCommand InCommand InCommand InCommand InCommand InCommand InData# PollingQ7Command InCommand InCommand InCommand InCommand InCommand InCommand InCommand #30HCommand InCommand #30HCommand #AAHCommand #55HCommand #80HCommand #AAHCommand #55HCommand #30H(Q0~Q7)Note:(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bitP/N:PM1200REV. 1.0, DEC. 20, 2005

28

MX29F400C T/BAUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART (WORD MODE)STARTWrite Data AAH Address 555HWrite Data 55H Address 2AAHWrite Data 80H Address 555HWrite Data AAH Address 555HWrite Data 55H Address 2AAHWrite Data 30H Sector AddressToggle Bit CheckingQ6 Toggled ?NOInvalid CommandYESLoad Other Sector Addrss If Necessary(Load Other Sector Address)Last Block to EraseYESNOTime-out Bit Checking Q3=1 ?NOYESNOToggle Bit CheckingQ6 not ToggledYESNOData# PollingQ7 = 1Q5 = 1YESResetAuto Block Erase CompletedAuto Block Erase ExceedTiming LimitP/N:PM1200REV. 1.0, DEC. 20, 2005

29

MX29F400C T/BERASE SUSPEND/ERASE RESUME FLOWCHARTSTARTWrite Data B0HERASE SUSPENDToggle Bit checking Q6 not toggledYESRead Array orProgramNOReading or Programming EndYESWrite Data 30HNODelay 400us (note)ERASE RESUMEContinue EraseAnotherErase Suspend ?YESNONote: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume isexceeded 1024 times, then the 400us time delay must be put into consideration.P/N:PM1200REV. 1.0, DEC. 20, 2005

30

MX29F400C T/BTIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12VA1A6Toggle bit pollingVerify 5VOE#tCEPWE#* See the following Note!CE#DataDon't care(Note 2)tOE01HF0HA18-A16Sector AddressNote1: Must issue \"unlock for sector protect/unprotect\" command before sector protection for a system without 12V provided.Note2: Except F0HP/N:PM1200REV. 1.0, DEC. 20, 2005

31

MX29F400C T/BTIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12VA1A6Toggle bit pollingVerify 5VOE#tCEPWE#* See the following Note!CE#DataDon't care(Note 2)tOE00HF0HNote1: Must issue \"unlock for sector protect/unprotect\" command before sector unprotection for a system without 12V provided.Note2: Except F0HP/N:PM1200REV. 1.0, DEC. 20, 2005

32

MX29F400C T/BSECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12VSTARTPLSCNT=1Write \"unlock for sector protect/unprotect\" Command(Table1)Set Up Sector Addr(A17,A16,A15,A14,A13,A12)OE#=VIH,A9=VIHCE#=VIL,A6=VILActivate WE# Pulse to startData don't careToggle bit checkingQ6 not ToggledYesIncrement PLSCNTSet CE#=OE#=VILA9=VIHNoNoRead from Sector Addr=SA, A1=1PLSCNT=32?NoData=01H?YesDevice FailedYesYesProtect Another Sector?NoWrite Reset CommandSector ProtectionCompleteP/N:PM1200REV. 1.0, DEC. 20, 2005

33

MX29F400C T/BCHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12VSTARTProtect All SectorsPLSCNT=1Write \"unlock for sector protect/unprotect\"Command (Table 1)Set OE#=A9=VIHCE#=VIL,A6=1Activate WE# Pulse to startData don't careNoToggle bit checkingQ6 not ToggledYesSet OE#=CE#=VILA9=VIH,A1=1IncrementPLSCNTSet Up First Sector AddrRead Data from DeviceNoIncrementSector AddrData=00H?NoPLSCNT=1000?YesNoYesDevice FailedAll sectors have been verified?YesWrite Reset CommandChip UnprotectComplete* It is recommended before unprotect whole chip, all sectors should be protected in advance.P/N:PM1200REV. 1.0, DEC. 20, 2005

34

MX29F400C T/BID CODE READ TIMING WAVEFORMVCC5VVIDADDA9VIHVILVIHVILADDA0tACCtACCADDA1-A8A10-A17CE#VIHVILVIHVILWE#VIHVILtCEOE#VIHVILtOEtDFtOHtOHDATAQ0-Q15VIHVILDATA OUTC2H/00C2HDATA OUT23H/ABH (Byte)2223H/22ABH (Word)P/N:PM1200REV. 1.0, DEC. 20, 2005

35

MX29F400C T/BERASE AND PROGRAMMING PERFORMANCE(1)

PARAMETER

Sector Erase TimeChip Erase TimeByte Programming TimeWord Programming TimeChip Programming Time

Byte ModeWord Mode

Erase/Program Cycles

100,000

MIN.

LIMITSTYP.(2)

0.749114.53

MAX.(3)

153230036013.59

UNITS

sec secusussecsecCycles

Note:

1.Not 100% Tested, Excludes external system level over head.2.Typical values measured at 25°C,5V.3.Maximum values measured at 25°C,4.5V.

LATCH-UP CHARACTERISTICS

MIN.

Input Voltage with respect to GND on all pins except I/O pinsInput Voltage with respect to GND on all I/O pinsCurrent

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

-1.0V-1.0V-100mA

MAX.13.5VVcc + 1.0V+100mA

DATA RETENTION

PARAMETERData Retention Time

MIN.20

UNITYears

P/N:PM1200REV. 1.0, DEC. 20, 2005

36

MX29F400C T/BORDERING INFORMATION

PART NO.

Access TimeOperating CurrentStandby CurrentTemperature

(ns)MAX.(mA)MAX.(uA)Range

MX29F400CTMI-55505-40oC~85oCMX29F400CTMI-7070405-40oC~85oCMX29F400CTMI-9090405-40oC~85oCMX29F400CTTI-55505-40oC~85oCMX29F400CTTI-70MX29F400CTTI-90MX29F400CBMI-55MX29F400CBMI-70MX29F400CBMI-90MX29F400CBTI-55MX29F400CBTI-70MX29F400CBTI-90MX29F400CTMI-55GMX29F400CTMI-70GMX29F400CTMI-90GMX29F400CTTI-55GMX29F400CTTI-70GMX29F400CTTI-90GMX29F400CBMI-55GMX29F400CBMI-70GMX29F400CBMI-90GMX29F400CBTI-55GMX29F400CBTI-70GMX29F400CBTI-90G

7090557090557090557090557090557090557090

4040404040404040404040404040404040404040

55555555555555555555

-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC-40oC~85oC

PACKAGE44 Pin SOP44 Pin SOP44 Pin SOP48 Pin TSOP(Normal Type)48 Pin TSOP(Normal Type)48 Pin TSOP(Normal Type)44 Pin SOP44 Pin SOP44 Pin SOP48 Pin TSOP(Normal Type)48 Pin TSOP(Normal Type)48 Pin TSOP(Normal Type)44 Pin SOP44 Pin SOP44 Pin SOP48 Pin TSOP(Normal Type)48 Pin TSOP(Normal Type)48 Pin TSOP(Normal Type)44 Pin SOP44 Pin SOP44 Pin SOP48 Pin TSOP(Normal Type)48 Pin TSOP(Normal Type)48 Pin TSOP(Normal Type)

Remark

PB-freePB-freePB-freePB-freePB-freePB-freePB-freePB-freePB-freePB-freePB-freePB-free

Note:The Automotive grade is under development.

P/N:PM1200REV. 1.0, DEC. 20, 2005

37

MX29F400C T/BPART NAME DESCRIPTIONMX29F400CTTI70GOPTION:G: Lead-free packageblank: normalSPEED:55:55ns70:70ns90: 90nsTEMPERATURE RANGE:I: Industrial (-40˚aC to 85˚ C)PACKAGE:M:SOPT: TSOPBOOT BLOCK TYPE:T: Top BootB: Bottom BootREVISION:CDENSITY & MODE:400: 4M, x8/x16 Boot SectorTYPE:F: 5VDEVICE:29: FlashP/N:PM1200REV. 1.0, DEC. 20, 2005

38

MX29F400C T/BPACKAGE INFORMATIONP/N:PM1200REV. 1.0, DEC. 20, 2005

39

MX29F400C T/BP/N:PM1200REV. 1.0, DEC. 20, 2005

40

MX29F400C T/BREVISION HISTORY

Revision No.Description1.01. Removed \"Preliminary\" title

2. Removed commercial grade

3. Added access time: 55ns; Removed access time: 120ns

PageP1AllAll

Date

DEC/20/2005

P/N:PM1200REV. 1.0, DEC. 20, 2005

41

MX29F400C T/BMACRONIX INTERNATIONAL CO., LTD.

Headquarters:

TEL:+886-3-578-6688FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020FAX:+32-2-456-8021

Office :

TEL:+86-755-834-335-79FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-60FAX:+81-6-4807-61

Singapore Office :

TEL:+65-6346-5505FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.