Clock signal generating circuit for digital signal

专利名称：Clock signal generating circuit for digital

signal recording device

发明人：Hidehiro Ishii申请号：US06/769646申请日：19850827公开号：US04729042A公开日：19880301

摘要：A clock signal generating circuit for a data reproducing device, such as a devicein which an audio signal is digitized and recorded in multiplex form together with othersignals such as video signals, on a magnetic recording medium, wherein the stability ofthe frequency of the clock signal is maintained even in the presence of drop- out of theaudio, video or other signals. The clock signal generating circuit includes a voltage-controlled oscillator receiving as a frequency- control input signal the output of a phasecomparator comparing the output of the voltage-controlled oscillator with a pulse trainsignal extracted from the RF signal read from the recording medium. The voltage-controlled oscillator receives a second control signal which causes it to maintain itspresent frequency. The second control signal is produced by ORing drop-out signalsgenerated when FM signals obtained by subjecting the video and audio signals tofrequency modulation are no longer present in the RF signal.

申请人：PIONEER ELECTRONIC CORPORATION

代理机构：Sughrue, Mion, Zinn, Macpeak, and Seas

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