专利名称:CMOS SRAM cells employing multiple-gate
transistors and methods fabricating thesame
发明人:Zong-Liang Huo,Seung-Jae Baik,In-Seok
Yeo,Hong-Sik Yoon,Shi-Eun Kim
申请号:US11375617申请日:20060314
公开号:US20060220134A1公开日:20061005
专利附图:
摘要:Complementary metal oxide semiconductor (CMOS) static random access
memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern ofstacked semiconductor regions of opposite conductivity type. In some of these
embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type)MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regionsof the first conductivity type MOS load transistor and the second conductivity type drivertransistor are vertically stacked relative to each other within a first portion of a verticaldual-conductivity semiconductor fin structure. This fin structure is surrounded on at leastthree sides by a wraparound gate electrode, which is configured to modulate conductivityof both the active regions in response to a gate signal.
申请人:Zong-Liang Huo,Seung-Jae Baik,In-Seok Yeo,Hong-Sik Yoon,Shi-Eun Kim
地址:Gyeonggi-do KR,Seoul KR,Seoul KR,Gyeonggi-do KR,Seoul KR
国籍:KR,KR,KR,KR,KR
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