专利名称：Method of generating test sequences发明人：Toshinori Hosokawa申请号：US09350523申请日：19990712公开号：US06449743B1公开日：20020910
专利附图：
摘要：Test sequences for use in fault testing for an integrated circuit are efficientlygenerated. The integrated circuit is subjected to timeframe expansion, thereby
generating a time expansion model including a combinational circuit. With respect to thistime expansion model, a compaction template is generated by compacting one or more
primitive templates indicating whether or not a primary input or a pseudo primary input ispresent in each time. Test patterns are generated with respect to the time expansionmodel, and the generated test patterns are transformed, with compaction accompanied,into test sequences. The compaction is conducted by substituting the respective testpatterns in the compaction template and connecting the resultant compactiontemplates. In this manner, short test sequences can be efficiently generated withoutspending much time on the compaction.
申请人：MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
代理机构：Nixon Peabody LLP
代理人：Donald R. Studebaker
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