MOTOROLASEMICONDUCTOR TECHNICAL DATAMC14513BBCD-To-Seven SegmentLatch/Decoder/DriverL SUFFIXCERAMICCASE 726P SUFFIXPLASTICCASE 707CMOS MSI (Low–Power Complementary MOS)The MC14513B BCD–to–seven segment latch/decoder/driver isconstructed with complementary MOS (CMOS) enhancement mode devicesand NPN bipolar output drivers in a single monolithic structure. The circuitprovides the functions of a 4–bit storage latch, an 8421 BCD–to–sevensegment decoder, and has output drive capability. Lamp test (LT), blanking(BI), and latch enable (LE) inputs are used to test the display, to turn–off orpulse modulate the brightness of the display, and to store a BCD code,respectively. The Ripple Blanking Input (RBI) and Ripple Blanking Output(RBO) can be used to suppress either leading or trailing zeroes. It can beused with seven–segment light emitting diodes (LED), incandescent,fluorescent, gas discharge, or liquid crystal readouts either directly orindirectly.Applications include instrument (e.g., counter, DVM, etc.) display driver,computer/calculator display driver, cockpit display driver, and various clock,watch, and timer uses.•••••••••••Low Logic Circuit Power DissipationHigh–current Sourcing Outputs (Up to 25 mA)Latch Storage of Binary InputBlanking InputLamp Test ProvisionReadout Blanking on all Illegal Input CombinationsLamp Intensity Modulation CapabilityTime Share (Multiplexing) CapabilityAdds Ripple Blanking In, Ripple Blanking Out to MC14511BSupply Voltage Range = 3.0 V to 18 VCapable of Driving Two Low–Power TTL Loads, One Low–powerSchottky TTL Load to Two HTL Loads Over the Rated TemperatureRange.ORDERING INFORMATIONMC14XXXBCPMC14XXXBCLPlasticCeramicTA = – 55° to 125°C for all packages.PIN ASSIGNMENTBCLTBILEDARBIVSS1234567181716151413121110VDDfgabcdeRBOedfagbcDISPLAY01234567MAXIMUM RATINGS* (Voltages Referenced to VSS)RatingDC Supply VoltageInput Voltage, All InputsDC Current Drain per Input PinOperating Temperature RangePower Dissipation, per Package†Storage Temperature RangeMaximum Continuous Output Drive Current(Source) per OutputMaximum Continuous Output Power(Source) per Output‡SymbolVDDVinITAPDTstgIOHmaxPOHmaxTRUTH TABLEValue– 0.5 to + 18– 0.5 to VDD +0.510– 55 to + 125500– 65 to + 1502550UnitVVmA°CmW_CmAmWXX10XXXXXXXXXXXXXXXXXX000000000000000001X0111111111111111111InputsRBILEBILT01111111111111111111OutputsDCBARBOabcdefgDisplayXXXXXXXX000000000 000000111111110 00111100001111011001100110011101010101010101++10000000000000000†1111111000000000000001111110011010111000000111101111000000101110111000000011011011000000*0100010100000000001110110000000111110110000008BlankBlank01234567BlankBlankBlankBlankBlankBlank*‡POHmax = IOH (VDD – VOH)*Maximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_CCeramic “L” Packages: – 12 mW/_C From 100_C To 125_CREV 31/94X X X XX = Don’t Care†RBO = RBI (D C B A), indicated by other rows of table*Depends upon the BCD code previously applied when LE = 0©MC14513B Motorola, Inc. 1995376MOTOROLA CMOS LOGIC DATAELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)CharacteristicOutput Voltage — Segment Outputs“0” LevelVin = VDD or 0“1” LevelVin = 0 or VDDOutput Voltage — RBO Output“0” LevelVin = VDD or 0“1” LevelVin = 0 or VDDInput Voltage #“0” Level(VO = 3.8 or 0.5 Vdc)(VO = 8.8 or 1.0 Vdc)(VO = 13.8 or 1.5 Vdc)(VO = 0.5 or 3.8 Vdc) “1” Level(VO = 1.0 or 8.8 Vdc)(VO = 1.5 or 13.8 Vdc)Output Drive Voltage — Segments(IOH = 0 mA) Source(IOH = 5.0 mA)(IOH = 10 mA)(IOH = 15 mA)(IOH = 20 mA)(IOH = 25 mA)(IOH = 0 mA)(IOH = 5.0 mA)(IOH = 10 mA)(IOH = 15 mA)(IOH = 20 mA)(IOH = 25 mA)(IOH = 0 mA)(IOH = 5.0 mA)(IOH = 10 mA)(IOH = 15 mA)(IOH = 20 mA)(IOH = 25 mA)VILVOLSymbolVOLVDDVdc5.010155.010155.010155.010155.010155.010155.0Min———4.19.114.1———4.959.9514.95———3.57.0114.1—3.9—3.4—9.1—9.0—8.6—14.1—14—13.6—– 55_CMax0.050.050.05———0.050.050.05———1.53.04.0—————————————————————Min———4.19.114.1———4.959.9514.95———3.57.0114.1—3.9—3.4—9.1—9.0—8.6—14.1—14—13.6—25_CTyp #0005.010150005.010152.2.506.752.755.508.2.574.244.123.943.703.9.5.269.179.048.908.7514.5914.2714.1814.0713.9513.80Max0.050.050.05———0.050.050.05———1.53.04.0—————————————————————125_CMin———4.19.114.1———4.959.9514.95———3.57.0114.1—3.5—3.0—9.1—8.6—8.2—14.1—13.6—13.2—Max0.050.050.05———0.050.050.05———1.53.04.0—————————————————————VdcVdcVdcVdcUnitVdcVOHVdcVOHVdcVIHVOHVdc1015Vdc(continued)This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; how-ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to thishigh-impedance circuit. A destructive high current mode may occur if Vin and Vout is not constrained to the range VSS ≤ (Vin orVout) ≤ VDD.Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted toVSS and are at a logical 1 (See Maximum Ratings).Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).MOTOROLA CMOS LOGIC DATAMC14513B377ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)CharacteristicOutput Drive Current — RBO Output(VOH = 2.5 V)Source(VOH = 9.5 V)(VOH = 13.5 V)(VOL = 0.4 V) (VOL = 0.5 V)(VOL = 1.5 V)SinkSymbolIOHVDDVdc5.010155.010155.0101515—5.010155.01015– 55_CMin– 0.40– 0.21– 0.810.180.471.800.1..2—————Max—————————± 0.1—5.01020Min– 0.32– 0.17– 0.660.150.381.500.511.33.4—————25_CTyp #– 0.– 0.34– 1.300.290.752.900.882.258.8±0.000015.00.0050.0100.015Max—————————± 0.17.55.01020125_CMin– 0.22– 0.12– 0.460.100.261.00.360.92.4—————Max—————————± 1.0—150300600µAdcpFµAdcmAdcUnitmAdcIOLOutput Drive Current — Segments(VOL = 0.4 V)Sink(VOL = 0.5 V)(VOL = 1.5 V)Input CurrentInput CapacitanceQuiescent Current(Per Package) Vin = 0 or VDD,Iout = 0 µATotal Supply Current**†(Dynamic plus Quiescent,Per Package) (CL = 50 pF on all outputs, all buffers switching)IOLmAdcIinCinIDDITIT = (1.9 µA/kHz) f + IDDIT = (3.8 µA/kHz) f + IDDIT = (5.7 µA/kHz) f + IDDµAdc#Noise immunity specified for worst–case input combination. Noise Margin for both “1” and “0” level = 1.0 Vdc min @ VDD = 5.0 Vdc2.0 Vdc min @ VDD = 10 Vdc 2.5 Vdc min @ VDD = 15 Vdc**āThe formulas given are for the typical characteristics only at 25_C.†To calculate total supply current at loads other than 50 pF:IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDfwhere: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.Input LE and RBI low, and Inputs D, BI and LT high.f in respect to a system clock.All outputs connected to respective CL loads.20 nsA, B, AND C90%50%12f20 ns10%VDDVSSVOHVOL50% DUTY CYCLEANY OUTPUT50%Figure 1. Dynamic Power Dissipation Signal WaveformsMC14513B378MOTOROLA CMOS LOGIC DATASWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)CharacteristicOutput Rise Time — Segment OutputsSymboltTLHVDDVdc5.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.01015All TypesMin——————————————————————————————1004030604030520220130Typ4030280240190125756527013511002501757202902006002001504852001603131259031312590——————26011065Max806050ns960480380ns250150130ns0270220ns12805003501440580400750300220970400320625250180625250180—————————nsnsnsUnitnsOutput Rise Time — RBO OutputtTLHOutput Fall Time — Segment Outputs*tTHL = (1.5 ns/pF) CL + 50 nstTHL = (0.75 ns/pF) CL + 37.5 nstTHL = (0.55 ns/pF) CL + 37.5 nsOutput Fall Time — RBO OutputstTHL = (3.25 ns/pF) CL + 107.5 nstTHL = (1.35 ns/pF) CL + 67.5 nstTHL = (0.95 ns/pF) CL + 62.5 nsPropagation Delay Time — A, B, C, D Inputs*tPLH = (0.40 ns/pF) CL + 620 nstPLH = (0.25 ns/pF) CL + 237.5 nstPLH = (0.20 ns/pF) CL + 165 nstPHL = (1.3 ns/pF) CL + 655 nstPHL = (0.60 ns/pF) CL + 260 nstPHL = (0.35 ns/pF) CL + 182.5 nsPropagation Delay Time — RBI and BI Inputs* Inputs*tPLH = (1.05 ns/pF) CL + 7.5 nstPLH = (0.45 ns/pF) CL + 177.5 nstPLH = (0.30 ns/pF) CL + 135 nstPHL = (0.85 ns/pF) CL + 442.5 nstPHL = (0.45 ns/pF) CL + 177.5 nstPHL = (0.35 ns/pF) CL + 142.5 nsPropagation Delay Time — LT Input* Input*tPLH = (0.45 ns/pF) CL + 290.5 nstPLH = (0.25 ns/pF) CL + 112.5 nstPLH = (0.20 ns/pF) CL + 80 nstPHL = (1.3 ns/pF) CL + 248 nstPHL = (0.45 ns/pF) CL + 102.5 nstPHL = (0.35 ns/pF) CL + 72.5 nsSetup TimetTHLtTHLtPLHtPHLtPLHnstPHLtPLHnstPHLtsunsHold TimethnsLatch Enable Pulse WidthtWL(LE)ns*The formulas given are for the typical characteristics only.MOTOROLA CMOS LOGIC DATAMC14513B37920 nsINPUT CtPLHOUTPUT g90%50%10%tPHL20 nsVDDVSSVOHVOLtTLHtTHLa. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.20 nsINPUT CtPLHOUTPUT RBOtTLH50%90%50%10%tPHL90%10%tTHL20 nsVDDVSSVOHVOLb. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.20 nsLE10%tsuINPUT C50%VSSVOHOUTPUT gVOL90%50%thVDDVSSVDDc. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.20 ns90%50%LEtWL(LE)10%20 nsVDDVSSd. Pulse Width: Data DCBA strobed into latches.Figure 2. Dynamic Signal WaveformsMC14513B380MOTOROLA CMOS LOGIC DATACONNECTIONS TO VARIOUS DISPLAY READOUTSLIGHT EMITTING DIODE (LED) READOUTVDDVDDCOMMONCATHODE LEDCOMMONANODE LED≈ 1.7 V≈ 1.7 VVSSVSSINCANDESCENT READOUTVDDVDDFLUORESCENT READOUTVDD* *DIRECT(LOW BRIGHTNESS)FILAMENT(SUPPLY)VSSVSSVSS OR APPROPRIATEVOLTAGE BELOW VSS.GAS DISCHARGE READOUTVDDAPPROPRIATEVOLTAGELIQUID CRYSTAL (LC) READOUTEXCITATION(SQUARE WAVE,VSS TO VDD)VDD1/4 OF MC14070BVSS**A filament pre–warm resistor is recommended to reducefilament thermal shock and increase the effective coldresistance of the filament.VSSDirect dc drive of LC’s not recommended for life of LC readouts.MOTOROLA CMOS LOGIC DATAMC14513B381LOGIC DIAGRAMBI415aA714b13cB112d11e17fC216gLT30D6RBI810RBOLE5TYPICAL APPLICATIONS FOR RIPPLE BLANKINGLEADING EDGE ZERO SUPPRESSIONDISPLAYSCONNECT TOa–––––gRBO1BAa–––––gRBIDCRBOBA1a–––––gRBIDCRBOBA0a–––––gRBIDCBRBOA0a–––––gRBIDCBRBOA0a–––––gRBIDCBRBOA0RBIVDD (1)DCMC14513BINPUTCODE00(0)000MC14513B0(0)000MC14513B1(5)010MC14513B0(0)000MC14513B0(1)010MC14513B0(3)11MC14513B382MOTOROLA CMOS LOGIC DATATYPICAL APPLICATIONS FOR RIPPLE BLANKING (Cont)TRAILING EDGE ZERO SUPPRESSIONDISPLAYS0a–––––gRBODCRBIBA0a–––––gRBODCRBIBA0a–––––gRBODCRBIBA0a–––––gRBODCRBIBA1a–––––gRBODCBRBIA1a–––––gRBODCBRBIACONNECT TOVDD (1)MC14513B01(5)010MC14513B0(0)000MC14513B0(1)010MC14513B0(3)110MC14513B0(0)000MC14513B0(0)00INPUT CODEMOTOROLA CMOS LOGIC DATAMC14513B383OUTLINE DIMENSIONSL SUFFIXCERAMIC DIP PACKAGECASE 726–04ISSUE G–A–1810NOTES:1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4.DIMENSION F FOR FULL LEADS. HALFLEADS OPTIONAL AT LEAD POSITIONS 1, 9,10, AND 18.DIMABCDFGJKLMNSINCHESMINMAX0.8800.9100.2400.295–––0.2000.0150.0210.0550.0700.100 BSC0.0080.0120.1250.1700.300 BSC0 _15 _0.0200.040MILLIMETERSMINMAX22.3523.116.107.49–––5.080.380.531.401.782. BSC0.200.303.184.327.62 BSC0 _15 _0.511.02–B–19OPTIONAL LEADCONFIGURATION (1, 9, 10, 18)LCN–T–SEATINGPLANEKFGD18 PL0.25 (0.010)JM18 PLMMTAS0.25 (0.010)TBP SUFFIXPLASTIC DIP PACKAGECASE 707–02ISSUE C18110B9NOTES:1.POSITIONAL TOLERANCE OF LEADS (D),SHALL BE WITHIN 0.25 (0.010) AT MAXIMUMMATERIAL CONDITION, IN RELATION TOSEATING PLANE AND EACH OTHER.2.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.3.DIMENSION B DOES NOT INCLUDE MOLDFLASH.DIMABCDFGHJKLMNMILLIMETERSMINMAX22.2223.246.106.603.5.570.360.561.271.782. BSC1.021.520.200.302.923.437.62 BSC0 _15 _0.511.02INCHESMINMAX0.8750.9150.2400.2600.1400.1800.0140.0220.0500.0700.100 BSC0.0400.0600.0080.0120.1150.1350.300 BSC0 _15 _0.0200.040ACLNFHGDSEATINGPLANEKMJHow to reach us:
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MC14513B384
MOTOROLA CMOS LOGIC DATA
