MC14001B

B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,MC14025B, MC14071B, MC14073B,MC14081B, MC14082B

The B Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure(Complementary MOS). Their primary use is where low powerdissipation and/or high noise immunity is desired.

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MARKINGDIAGRAMS14PDIP–14P SUFFIXCASE 6MC140xxBCPAWLYYWW114SOIC–14D SUFFIXCASE 751A114TSSOP–14DT SUFFIXCASE 948G114SOEIAJ–14F SUFFIXCASE 9651xxAWL, LYY, YWW, W= Specific Device Code= Assembly Location= Wafer Lot= Year= Work WeekMC140xxBALYW140xxBALYW140xxBAWLYWW•Supply Voltage Range = 3.0 Vdc to 18 Vdc•All Outputs Buffered

•Capable of Driving Two Low–power TTL Loads or One Low–power••

Schottky TTL Load Over the Rated Temperature Range.Double Diode Protection on All Inputs Except: Triple DiodeProtection on MC14011B and MC14081B

Pin–for–Pin Replacements for Corresponding CD4000 Series BSuffix Devices

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)

SymbolVDDVin, VoutIin, IoutPDTATstgTLParameterDC Supply Voltage RangeInput or Output Voltage Range(DC or Transient)Input or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)Ambient Temperature RangeStorage Temperature RangeLead Temperature(8–Second Soldering)Value–0.5 to +18.0–0.5 to VDD + 0.5±10500–55 to +125–65 to +150260UnitVVmAmW°C°C°CDEVICE INFORMATION

DeviceMC14001BMC14011BMC14023BMC14025BMC14071BMC14073BMC14081BMC14082B

Description

Quad 2–Input NOR GateQuad 2–Input NAND GateTriple 3–Input NAND GateTriple 3–Input NOR GateQuad 2–Input OR GateTriple 3–Input AND GateQuad 2–Input AND GateDual 4–Input AND Gate

1.Maximum Ratings are those values beyond which damage to the devicemay occur.

2.Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, Vin and Vout should be constrainedto the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either VSS or VDD). Unused outputs must be left open.

ORDERING INFORMATION

See detailed ordering and shipping information in the packagedimensions section on page 11 of this data sheet.

© Semiconductor Components Industries, LLC, 20001

August, 2000 – Rev. 2

Publication Order Number:

MC14001B/D

MC14001B Series

LOGIC DIAGRAMS

NOR

MC14001BQuad 2–Input NOR Gate12

NAND

MC14011BQuad 2–Input NAND Gate12561213OR

MC14071BQuad 2–Input OR Gate12561213AND

MC14081BQuad 2–Input AND Gate1256121334343434

2 INPUT561213

1011101110111011

MC14025BTriple 3–Input NOR Gate128345111213

9610MC14023BTriple 3–Input NAND Gate1283451112139610MC14073BTriple 3–Input AND Gate1283451112139610MC14082BDual 4–Input AND Gate234591011121

3 INPUT13

NC = 6, 8VDD = PIN 14VSS = PIN 7FOR ALL DEVICES

PIN ASSIGNMENTS

MC14001B

Quad 2–Input NOR Gate

IN 1AIN 2AOUTAOUTBIN 1BIN 2BVSS

1234567141312111098VDDIN 2DIN 1DOUTDOUTCIN 2CIN 1C

MC14011B

Quad 2–Input NAND Gate

IN 1AIN 2AOUTAOUTBIN 1BIN 2BVSS

1234567141312111098VDDIN 2DIN 1DOUTDOUTCIN 2CIN 1C

MC14023B

Triple 3–Input NAND Gate

IN 1AIN 2AIN 1BIN 2BIN 3BOUTBVSS

1234567141312111098VDDIN 3CIN 2CIN 1COUTCOUTAIN 3A

MC14025B

Triple 3–Input NOR Gate

IN 1AIN 2AIN 1BIN 2BIN 3BOUTBVSS

1234567141312111098VDDIN 3CIN 2CIN 1COUTCOUTAIN 3A

MC14071B

Quad 2–Input OR Gate

IN 1AIN 2AOUTAOUTBIN 1BIN 2BVSS

1234567141312111098VDDIN 2DIN 1DOUTDOUTCIN 2CIN 1C

MC14073B

Triple 3–Input AND Gate

IN 1AIN 2AIN 1BIN 2BIN 3BOUTBVSS

1234567141312111098VDDIN 3CIN 2CIN 1COUTCOUTAIN 3A

MC14081B

Quad 2–Input AND Gate

IN 1AIN 2AOUTAOUTBIN 1BIN 2BVSS

1234567141312111098VDDIN 2DIN 1DOUTDOUTCIN 2CIN 1C

MC14082B

Dual 4–Input AND Gate

OUTAIN 1AIN 2AIN 3AIN 4ANCVSS

1234567141312111098VDDOUTBIN 4BIN 3BIN 2BIN 1BNC

NC = NO CONNECTION

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MC14001B Series

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)CharacteristicSymbolVOLVDDVdc5.010155.010155.010155.010155.05.010155.0101515—– 55_CMin———25_C125_CMaxMin———Typ (3.)000MaxMin———MaxUnitVdcOutput VoltageVin = VDD or 0“0” Level0.050.050.05———0.050.050.05———0.050.050.05———“1” LevelVOHVin = 0 or VDD4.959.9514.95———4.959.9514.95———5.0101.959.9514.95———VdcInput Voltage“0” Level(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)“1” Level(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)VIL1.53.04.0——————————2.2.506.752.755.508.251.53.04.0——————————1.53.04.0——————————VdcVIH3.57.0113.57.0113.57.011VdcOutput Drive Current(VOH = 2.5 Vdc) (VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)(VOL = 0.4 Vdc) (VOL = 0.5 Vdc)(VOL = 1.5 Vdc)IOHSource– 3.0– 0.– 1.6– 4.20.1..2—————– 2.4– 0.51– 1.3– 3.40.511.33.4—————– 4.2– 0.88 – 2.25– 8.80.882.258.8– 1.7– 0.36– 0.9– 2.40.360.92.4—————mAdcSinkIOLmAdcInput CurrentIin± 0.1—±0.000015.0± 0.17.5± 1.0—µAdcpFInput Capacitance(Vin = 0)CinQuiescent Current(Per Package)IDD5.010155.010150.250.51.00.00050.00100.00150.250.51.07.51530µAdcTotal Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Gate, CL = 50 pF)ITIT = (0.3 µA/kHz) f + IDD/NIT = (0.6 µA/kHz) f + IDD/NIT = (0.9 µA/kHz) f + IDD/NµAdc3.Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4.The formulas given are for the typical characteristics only at 25_C.5.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gatesper package.

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MC14001B Series

B–SERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)CharacteristicSymboltTLHVDDVdc5.010155.01015Min——————Typ (7.)10050401005040Max2001008020010080UnitnsOutput Rise Time, All B–Series GatestTLH = (1.35 ns/pF) CL + 33 nstTLH = (0.60 ns/pF) CL + 20 nstTLH = (0.40 ns/PF) CL + 20 nsOutput Fall Time, All B–Series GatestTHL = (1.35 ns/pF) CL + 33 nstTHL = (0.60 ns/pF) CL + 20 nstTHL = (0.40 ns/pF) CL + 20 nstTHLnsPropagation Delay TimeMC14001B, MC14011B onlytPLH, tPHL = (0.90 ns/pF) CL + 80 nstPLH, tPHL = (0.36 ns/pF) CL + 32 nstPLH, tPHL = (0.26 ns/pF) CL + 27 nsAll Other 2, 3, and 4 Input GatestPLH, tPHL = (0.90 ns/pF) CL + 115 nstPLH, tPHL = (0.36 ns/pF) CL + 47 nstPLH, tPHL = (0.26 ns/pF) CL + 37 ns8–Input Gates (MC14068B, MC14078B)tPLH, tPHL = (0.90 ns/pF) CL + 155 nstPLH, tPHL = (0.36 ns/pF) CL + 62 nstPLH, tPHL = (0.26 ns/pF) CL + 47 nstPLH, tPHL5.010155.010155.01015—————————12550401606550200806025010080300130100350150110ns6.The formulas given are for the typical characteristics only at 25_C.7.Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

14PULSEGENERATORINPUTVDD20 nsINPUT

OUTPUT

tPHLOUTPUTINVERTING

90%50%10%90%50%10%tTHLtPLH20 nsVDD0 VtPLHVOH

tTLHtPHLVOLVOHVOL

*CL7VSS*All unused inputs of AND, NAND gates must be connected to VDD.All unused inputs of OR, NOR gates must be connected to VSS.

OUTPUTNON-INVERTINGtTLH90%50%10%tTHLFigure 1. Switching Time Test Circuit and Waveforms

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MC14001B Series

CIRCUIT SCHEMATICNOR, OR GATES

MC14001B, MC14071BOne of Four Gates Shown

VDD1, 6, 8, 132, 5, 9, 12*14VDDMC14025B

One of Three Gates Shown

VDD1, 3, 112, 4, 123, 4, 10, 11*7VSSVSSVDD8, 5, 137VSS

VSS9, 6, 10

14VDDVSS*Inverter omitted in MC14001B*Inverter omitted in MC14025B

CIRCUIT SCHEMATICNAND, AND GATES

MC14023B, MC14073BOne of Three Gates Shown

VDD*3, 4, 10, 11

2, 4, 121, 3, 1114VSSVDD8, 5, 137*Inverter omitted in MC14023B

VSSVDD2, 5, 9, 121, 6, 8, 13*9, 6, 10MC14011B, MC14081BOne of Four Gates Shown

14VDD7VSS*Inverter omitted in MC14011BVSS

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MC14001B Series

TYPICAL B–SERIES GATE CHARACTERISTICS

N–CHANNEL DRAIN CURRENT (SINK)

5.04.03.02.01.00TA = - 55°C- 40°C+ 85°C+ 25°C+ 125°C- 10- 9.0

I ,DRAIN CURRENT (mA)DI ,DRAIN CURRENT (mA)D- 8.0- 7.0- 6.0- 5.0- 4.0- 3.0- 2.0- 1.0

01.02.03.04.0VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

5.000- 1.0- 2.0- 3.0- 4.0VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

- 5.0+ 85°CTA = - 55°C- 40°C+ 25°CP–CHANNEL DRAIN CURRENT (SOURCE)

+ 125°CFigure 2. VGS = 5.0 Vdc

2018I ,DRAIN CURRENT (mA)D161412108.06.04.02.0001.02.03.04.05.06.07.08.0VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

9.010TA = - 55°C- 40°C+ 25°C+ 85°C+ 125°C- 50- 45I ,DRAIN CURRENT (mA)D- 40- 35- 30- 25- 20- 15- 10- 5.000Figure 3. VGS = – 5.0 Vdc

TA = - 55°C+ 25°C- 40°C+ 85°C+ 125°C- 1.0- 2.0- 3.0- 4.0- 5.0- 6.0- 7.0- 8.0- 9.0- 10VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

Figure 4. VGS = 10 Vdc

5040I ,DRAIN CURRENT (mA)D3530252015105.0002.04.06.08.010121416VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

1820I ,DRAIN CURRENT (mA)DTA = - 55°C- 40°C+ 25°C+ 125°C+ 85°C- 100- 90- 80- 70- 60- 50- 40- 30- 20- 1000Figure 5. VGS = – 10 Vdc

TA = - 55°C+ 25°C- 40°C+ 85°C+ 125°C- 2.0- 4.0- 6.0- 8.0- 10- 12- 14- 16VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

- 18- 20Figure 6. VGS = 15 VdcFigure 7. VGS = – 15 Vdc

These typical curves are not guarantees, but are design aids.Caution: The maximum rating for output current is 10 mA per pin.

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MC14001B Series

TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

V o u t ,OUTPUT VOLTAGE (Vdc)5.04.03.02.01.0001.02.0SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORV o u t ,OUTPUT VOLTAGE (Vdc)108.06.04.02.0002.04.0SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORSINGLE INPUT NOR, ORMULTIPLE INPUT NAND, ANDSINGLE INPUT NOR, ORMULTIPLE INPUT NAND, AND3.04.05.0Vin, INPUT VOLTAGE (Vdc)6.08.010Vin, INPUT VOLTAGE (Vdc)

Figure 8. VDD = 5.0 VdcFigure 9. VDD = 10 Vdc

16V o u t ,OUTPUT VOLTAGE (Vdc)1412108.06.04.02.0002.04.0SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORSINGLE INPUT NOR, ORMULTIPLE INPUT NAND, ANDDC NOISE MARGIN

The DC noise margin is defined as the input voltage rangefrom an ideal “1” or “0” input level which does not produceoutput state change(s). The typical and guaranteed limitvalues of the input values VIL and VIH for the output(s) tobe at a fixed voltage VO are given in the ElectricalCharacteristics table. VIL and VIH are presented graphicallyin Figure 11.

Guaranteed minimum noise margins for both the “1” and“0” levels =

1.0 V with a 5.0 V supply2.0 V with a 10.0 V supply2.5 V with a 15.0 V supply

6.08.010Vin, INPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

VoutVO

VDDVoutVO

VDDVO

VDD0VIL

VIH

VinVO

VDD0VIL

VIH

VinVSS = 0 VOLTS DC

(a) Inverting Function(b) Non–Inverting Function

Figure 11. DC Noise Immunity

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MC14001B Series

PACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 6–06ISSUE M

148B17NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.INCHESMILLIMETERSMINMAXMINMAX0.7150.77018.1618.800.2400.2606.106.600.1450.1853.694.690.0150.0210.380.530.0400.0701.021.780.100 BSC2. BSC0.0520.0951.322.410.0080.0150.200.380.1150.1352.923.430.2900.3107.377.87---10 ---10 __0.0150.0390.381.01AFN–T–SEATINGPLANELCHGD14 PLKMJMDIMABCDFGHJKLMN0.13 (0.005)D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

–A–148NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

–B–17P7 PL0.25 (0.010)MBMGC–T–SEATINGPLANERX 45_FD14 PL0.25 (0.010)MKTBSMASJDIMABCDFGJKMPRMILLIMETERSMINMAX8.558.753.804.001.351.750.350.490.401.251.27 BSC0.190.250.100.250 7 __5.806.200.250.50INCHESMINMAX0.3370.3440.1500.1570.00.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090 7 __0.2280.2440.0100.019http://onsemi.com

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MC14001B Series

PACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

14X REFK

NOTES:

ąă1.DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

ąă2.CONTROLLING DIMENSION: MILLIMETER.ąă3.DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS. MOLDFLASH OR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.

ąă4.DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.

ąă5.DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.

ąă6.TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

ąă7.DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

DIMABCDFGHJJ1KK1LMMILLIMETERSMINMAX4.905.104.304.50---1.200.050.150.500.750.65 BSC0.500.600.090.200.090.160.190.300.190.256.40 BSC0 8 __INCHESMINMAX0.1930.2000.1690.177---0.0470.0020.0060.0200.0300.026 BSC0.0200.0240.0040.0080.0040.0060.0070.0120.0070.0100.252 BSC0 8 __0.10 (0.004)0.15 (0.006)TUSMTUSVNS2XL/21480.25 (0.010)MLPIN 1IDENT.17B–U–NFDETAIL EKK1JJ10.15 (0.006)TUSA–V–SECTION N–N–W–C0.10 (0.004)–T–SEATINGPLANEDGHDETAIL Ehttp://onsemi.com

9

MC14001B Series

PACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01ISSUE O

148LEQ1EHEM_LDETAIL P17ZDeAVIEW PNOTES:

ąă1.DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

ąă2.CONTROLLING DIMENSION: MILLIMETER.ąă3.DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.ąă4.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.ąă5.THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).DIMAA1bcDEeHE0.50LEMQ1ZMILLIMETERSMINMAX---2.050.050.200.350.500.180.279.9010.505.105.451.27 BSC7.408.200.500.851.101.500 _10 _0.700.90---1.42INCHESMINMAX---0.0810.0020.0080.0140.0200.0070.0110.3900.4130.2010.2150.050 BSC0.2910.3230.0200.0330.0430.0590 _10 _0.0280.035---0.056cb0.13 (0.005)MA10.10 (0.004)http://onsemi.com

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MC14001B Series

ORDERING & SHIPPING INFORMATION:

DeviceMC14001BCPMC14001BDMC14001BDR2MC14001BDTMC14001BDTR2PackagePDIP–14SOIC–14SOIC–14TSSOP–14TSSOP–14Shipping2000 Units per Box2750 Units per Box2500 Units / Tape & Reel96 Units per Rail96 Units per RailORDERING & SHIPPING INFORMATION:

DeviceMC14071BCPMC14071BDMC14071BDR2MC14071BDTMC14071BDTR2PackagePDIP–14SOIC–14SOIC–14TSSOP–14TSSOP–14Shipping2000 Units per Box55 Units per Rail2500 Units / Tape & Reel96 Units per Rail96 Units per RailMC14011BCPMC14011BDMC14011BDR2MC14011BDTMC14011BDTELMC14011BDTR2PDIP–14SOIC–14SOIC–14TSSOP–14TSSOP–14TSSOP–142000 Units per Box2750 Units per Box2500 Units / Tape & Reel96 Units per Rail2000 Units / Tape & Reel50 Units per RailMC14073BCPMC14073BDMC14073BDR2PDIP–14SOIC–14SOIC–142000 Units per Box55 Units per Rail2500 Units / Tape & ReelMC14081BCPMC14081BDMC14081BDR2PDIP–14SOIC–14SOIC–14TSSOP–14TSSOP–142000 Units per Box55 Units per Rail2500 Units / Tape & Reel96 Units per Rail2500 Units / Tape & ReelMC14023BCPMC14023BDMC14023BDR2PDIP–14SOIC–14SOIC–142000 Units per Box2750 Units per Box2500 Units / Tape & ReelMC14081BDTMC14081BDTR2MC14082BCPMC14025BCPMC14025BDMC14025BDR2PDIP–14SOIC–14SOIC–142000 Units per Box2750 Units per Box2500 Units / Tape & ReelMC14082BDMC14082BDR2PDIP–14SOIC–14SOIC–142000 Units per Box55 Units per Rail2500 Units / Tape & ReelFor ordering information on the EIAJ version of the SOIC pack-ages, please contact your local ON Semiconductor representa-tive.

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MC14001B Series

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

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ON Semiconductor Website: http://onsemi.comFor additional information, please contact your localSales Representative.http://onsemi.com12MC14001B/D