Power saving methods and apparatus to selectively

专利名称：Power saving methods and apparatus to

selectively enable cache bits based onknown processor state

发明人：Brian Michael Stempel,James Norris

Dieffenderfer,Jeffrey Todd Bridges,RodneyWayne Smith,Thomas Andrew Sartorius

申请号：US11073284申请日：20050304公开号：US07421568B2公开日：20080902

专利附图：

摘要：A processor capable of fetching and executing variable length instructions isdescribed having instructions of at least two lengths. The processor operates in multiplemodes. One of the modes restricts instructions that can be fetched and executed to thelonger length instructions. An instruction cache is used for storing variable lengthinstructions and their associated predecode bit fields in an instruction cache line andstoring the instruction address and processor operating mode state information at thetime of the fetch in a tag line. The processor operating mode state information indicatesthe program specified mode of operation of the processor. The processor fetches

instructions from the instruction cache for execution. As a result of an instruction fetchoperation, the instruction cache may selectively enable the writing of predecode bit fieldsin the instruction cache and may selectively enable the reading of predecode bit fieldsstored in the instruction cache based on the processor state at the time of the fetch.

申请人：Brian Michael Stempel,James Norris Dieffenderfer,Jeffrey ToddBridges,Rodney Wayne Smith,Thomas Andrew Sartorius

地址：Raleigh NC US,Apex NC US,Raleigh NC US,Raleigh NC US,Raleigh NC US

国籍：US,US,US,US,US

代理人：Nicholas J. Pauley,Joseph B. Agusta,Thomas Rouse

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