元器件交易网www.cecb2b.com SN74F163A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS088 – MARCH 1987 – REVISED OCTOBER 1993•••• Internal Look-Ahead Circuitry for FastCountingCarry Output for N-Bit CascadingFully Synchronous Operation for CountingPackage Options Include PlasticSmall-Outline Packages and StandardPlastic 300-mil DIPsD OR N PACKAGE(TOP VIEW)descriptionThis synchronous, presettable, 4-bit binarycounter features an internal carry look-aheadcircuitry for application in high-speed countingdesigns. Synchronous operation is provided byhaving all flip-flops clocked simultaneously so that the outputs change coincident with each other when soinstructed by the count enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates theoutput counting spikes that are normally associated with asynchronous (ripple-clock) counters; however,counting spikes may occur on the ripple carry (RCO) output. A buffered clock (CLK) input triggers the fourflip-flops on the rising (positive-going) edge of the clock input waveform.CLRCLKABCDENPGND123456716151413121110VCCRCOQAQBQCQDENTLOADThis counter is fully programmable; that is, it may be preset to any number between 0 and 15. As presetting issynchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs toagree with the setup data after the next clock pulse regardless of the levels of the enable inputs.The clear function for the SN74F163A is synchronous and a low level at the clear (CLR) input sets all four ofthe flip-flop outputs low after the next low-to-high transition of the clock regardless of the levels of the enableinputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for themaximum count desired. The active-low output of the gate used for decoding is connected to the clear input tosynchronously clear the counter to 0000 (LLLL).The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications withoutadditional gating. Instrumental in accomplishing this function are two count-enable (ENP, ENT) inputs and aripple-carry (RCO) output. Both ENP and ENT must be high to count, and ENT if fed forward to enable RCO.RCO thus enabled will produce a high-level pulse while the count is 15 (HHHH). The high-level overflowripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowedregardless of the level of the clock input.The SN74F163A features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) thatwill modify the operating mode have no effect on the contents of the counter until clocking occurs. The functionof the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meetingthe setup and hold times.The SN74F163A is characterized for operation from 0°C to 70°C.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1993, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•2–1元器件交易网www.cecb2b.comSDFS088 – MARCH 1987 – REVISED OCTOBER 1993SN74F163ASYNCHRONOUS 4-BIT BINARY COUNTER state diagramCTRDIV165CT = 0M1M2G3G4C5/2,3,4+1, 5D124814131211QAQBQCQD121110981371461501234logic symbol†CLRLOADENTENPCLKABCD19107234563CT = 15RCO155†This symbol is in accordance with ANSI/IEEE Std 91-1984 andIEC Publication 617-12.2–2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN74F163A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS088 – MARCH 1987 – REVISED OCTOBER 1993logic diagram (positive logic)CLRLOADENTENP1910715RCO3R23G21, 2T/C31, 3DM114QACLKA3RG21, 2T/C3B41, 3DM113QB3RG21, 2T/C3C51, 3DM112QC3RG21, 2T/C3D61, 3DM111QDPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•2–3元器件交易网www.cecb2b.comSDFS088 – MARCH 1987 – REVISED OCTOBER 1993SN74F163ASYNCHRONOUS 4-BIT BINARY COUNTER logic symbol, each flip-flopRTECLKDLOAD3RG21, 2T/C31, 3DM1Q1Q1Q2Q2logic diagram, each flip-flop (positive logic)RTE(ToggleEnable)CLKQ1Q2DLOAD2–4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN74F163A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS088 – MARCH 1987 – REVISED OCTOBER 1993typical clear, preset, count, and inhibit sequencesIllustrated below is the following sequence:1.Clear outputs to zero2.Preset to binary twelve3.Count to thirteen, fourteen, fifteen, zero, one, and two4.InhibitCLRLOADABCDCLKENPENTQADataOutputsQBQCQDRCO12131415012InhibitCountSyncPresetClearAsyncClearDataInputsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•2–5元器件交易网www.cecb2b.comSDFS088 – MARCH 1987 – REVISED OCTOBER 1993SN74F163ASYNCHRONOUS 4-BIT BINARY COUNTER absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 VInput current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mAVoltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCCurrent into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mAOperating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°CStorage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1:The input voltage ratings may be exceeded provided the input current ratings are observed.recommended operating conditionsMINVCCVIHVILIIKIOHIOLTASupply voltageHigh-level input voltageLow-level input voltageInput clamp currentHigh-level output currentLow-level output currentOperating free-air temperature04.520.8–18–12070NOM5MAX5.5UNITVVVmAmAmA°Celectrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERVIKVOHVOLIIIIHENP, CLK, A, B, C, DIILENT, LOADCLRIOS§VCC = 5.5 V,VO = 0–60ICCVCC = 5.5 V37‡All typical values are at VCC = 5 V, TA = 25°C.§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.VCC = 5.5 V,VI = 0.5 VVCC = 4.5 V,VCC = 4.5 V,VCC = 4.75 V,VCC = 4.5 V,VCC = 5.5 V,VCC = 5.5 V,TEST CONDITIONSII = –18 mAIOH = –1 mAIOH = –1 mAIOL = 20 mAVI = 7 VVI = 2.7 VMIN2.52.70.30.50.120–0.6–1.2–1.2–15055mAmAmATYP‡3.4MAX–1.2UNITVVVmAµA2–6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN74F163A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS088 – MARCH 1987 – REVISED OCTOBER 1993timing requirements over recommended ranges of supply voltage and operating free-airtemperature (unless otherwise noted)VCC = 5 V,TA = 25°CMINfclocktwClock frequencyCLK high or low (loading)Pulse durationCLK(counting)CLK (counting)Data before CLK↑tsuSetup timeLOADandCLRbeforeCLK↑LOAD and CLR before CLKENPandENTbeforeCLK↑ENP and ENT before CLKData after CLK↑thHoldtimeHold timeLOADandCLRafterCLK↑LOAD and CLR after CLKENP and ENT after CLK↑HighLowHigh or lowHighLowHighLowHigh or lowHighLowHigh or low065118.51152200MAX10007511.59.511.552200nsnsns90MHzMINMAXUNITswitching characteristics (see Note 2)FROM(INPUT)TO(OUTPUT)VCC = 5 V,CL = 50 pF,RL = 500 Ω,TA = 25°CMINfmaxtPLHtPHLtPLHtPHLtPLHtPHLtPLH100CLK(LOADhigh)CLK (LOAD high)CLK(LOADlow)CLK (LOAD low)CLKENTAnyQAny QAnyQAny QRCORCO2.72.73.23.24.24.21.7TYP1205.17.15.65.69.69..17.5108.58.514147.5MAXVCC = 4.5 V to 5.5 V,CL = 50 pF,RL = 500Ω,TA = MIN to MAX†MIN902.72.73.23.24.24.21.78.5119.59.515158.58.5MAXMHznsnsnsnsPARAMETERUNITtPHL1.74.17.51.7†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.NOTE 2:Load circuits and waveforms are shown in Section 1.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•2–7元器件交易网www.cecb2b.comSDFS088 – MARCH 1987 – REVISED OCTOBER 1993SN74F163ASYNCHRONOUS 4-BIT BINARY COUNTER 2–8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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