FPGA可编程逻辑器件芯片XC3S4000-5FG320C中文规格书

Table 36-3:

Default Traffic Generator Control Connection (Cont’d)

I/O

Width

0 = LINEAR

1 = PRBS (PRBS supported 8, 10, 23)2 = WALKING1

vio_tg_instr_data_mode

SignalDescription

Data mode to be programmed.

Default Value

3 = WALKING0

I

4

4 = HAMMER15 = HAMMER06 = Block RAM

7 = CAL_CPLX (Must be programmed along with victim mode CAL_CPLX)8-15 = Reserved

0 = Read Only (No data check)1 = Write Only (No data check)

Reserved signal. Tie to 0.

vio_tg_instr_rw_mode

I4

2 = Write/Read (Read performs after Write and data value is checked against expected write

Reserved signal.

data. For QDR II+ SRAM, one port is used for

Tie to 0.

write and another port is used for read.)3 = Write once and Read forever (Data check on Read data)4-15 = Reserved

Read/Write submode to be programmed.This is a submode option when

vio_tg_instr_rw_mode is set to \"WRITE_READ\" mode.

vio_tg_instr_rw_submode

I2

This mode is only valid for DDR3/DDR4 and RLDRAM 3. For QDR II+ and QDR-IV SRAM interfaces, this mode should be set to 0.WRITE_READ = 0; // Send all Write commands follow by Read commands defined in the instruction.

WRITE_READ_SIMULTANEOUSLY = 1; // Send Write and Read commands pseudo-randomly. Note that Write is always ahead of Read.

Reserved signal. Tie to 0.

UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021

Chapter 36:Traffic Generator

Table 36-3:

Default Traffic Generator Control Connection (Cont’d)

I/O

Width

Description

Victim mode to be programmed.

One victim bit could be programmed using global register vio_tg_victim_bit. The rest of the bits on signal bus are considered to be aggressors.

The following program options define aggressor behavior:NO_VICTIM = 0;

HELD1 = 1; // All aggressor signals held at 1HELD0 = 2; // All aggressor signals held at 0

vio_tg_instr_victim_mode

I

3

SignalDefault Value

NONINV_AGGR = 3; // All aggressor signals are same as victim

INV_AGGR = 4; // All aggressor signals are inversion of victim

DELAYED_AGGR = 5; // All aggressor signals are delayed version of victim (num of cycle of delay is programmed at vio_tg_victim_aggr_delay)

DELAYED_VICTIM = 6; // Victim signal is delayed version of all aggressors

CAL_CPLX = 7; Complex Calibration pattern (Must be programed along with Data Mode CAL_CPLX)

Reserved signal. Tie to 0.

vio_tg_instr_victim_aggr_delay

I5

Define aggressor/victim pattern to be N-delay cycle of victim/aggressor, where 0 ≤ N ≤ 24.Reserved signal. It is used when victim mode \"DELAY_AGGR\" or Tie to 0.\"DELAY VICTIM\" mode is used in traffic pattern.Victim bit behavior programmed.VICTIM_EXTERNAL = 0; // Use Victim bit provided in vio_tg_glb_victim_bit

vio_tg_instr_victim_select

I3

VICTIM_ROTATE4 = 1; // Victim bit rotates from

Reserved signal.

Bits[3:0] for every Nibble

VICTIM_ROTATE8 = 2; // Victim bit rotates from Bits[7:0] for every Byte

VICTIM_ROTATE_ALL = 3; // Victim bit rotates through all bits

Tie to 0.

vio_tg_instr_num_of_iter

I32

Number of Read/Write commands to issue (number of issue must be > 0 for each instruction programmed).

M = Number of NOP cycles in between Read/Write commands at user interface at general interconnect clock

N = Number of Read/Write commands before NOP cycle insertion at user interface at general interconnect clock

Reserved signal. Tie to 0.

vio_tg_instr_m_nops_btw_n_burst_m

I10

Reserved signal. Tie to 0.

UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021

Chapter 36:Traffic Generator

Table 36-3:

Default Traffic Generator Control Connection (Cont’d)

I/O

Width

Description

M = Number of NOP cycles in between Read/Write commands at user interface at general interconnect clock

N = Number of Read/Write commands before NOP cycle insertion at user interface at general interconnect clockNext instruction to run.

vio_tg_instr_nxt_instr

I

6

SignalDefault Value

vio_tg_instr_m_nops_btw_n_burst_n

I32

Reserved signal. Tie to 0.

To end traffic, next instruction should point at EXIT instruction.

6’b000000-6’b011111 – valid instruction6’b1????? – EXIT instruction

Reserved signal. Tie to 0.

PRBS Data Seed Programming

0 = Traffic Table Mode – Traffic Generator uses traffic patterns programmed in 32-entry Traffic tableReserved signal. 1 = Direct Instruction Mode – Traffic Generator Tie to 0.uses current traffic pattern presented at VIO interface

Seed number to be programmed.

Reserved signal. Tie to 0.Reserved signal. Tie to 0.

vio_tg_seed_program_en

I1

vio_tg_seed_numI8

vio_tg_seed_dataIPRBS DATA WIDTH

PRBS seed to be programmed for a selected seed number (vio_tg_seed_num). PRBS_DATA_WIDTH is by default 23.

PRBS_DATA_WIDTH can support 8, 10, and 23.

Global Registers

vio_tg_glb_victim_bit

vio_tg_glb_start_addr

II

8

APP_ADDR_WIDTH

Global register to define which bit in data bus is victim. It is used when victim mode is used in traffic pattern.

Global register to define Start address seed for Linear Address Mode.

Reserved signal. Tie to 0.Reserved signal. Tie to 0.

Use for QDR-IV to control different traffic setup when Write-Read mode is selected. 2'b00 = Both Port A and Port B send Write traffic, follow by Read traffic

vio_tg_glb_qdriv_rw_submode

I

2

2'b01 = Port A sends Write traffic, while Port B sends Read traffic simultaneously

2'b10 = Port B sends Write traffic, while Port A sends Read traffic simultaneously

2'b11 = Both Port A and Port B send a mix of Write and Read traffic. Only Linear address mode is supported.

UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021