DM7474

DM7474

Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

General Description

This device contains two independent positive-edge-trig-gered D-type flip-flops with complementary outputs. Theinformation on the D input is accepted by the flip-flops onthe positive going edge of the clock pulse. The triggeringoccurs at a voltage level and is not directly related to the

transition time of the rising edge of the clock. The data onthe D input may be changed while the clock is LOW orHIGH without affecting the outputs as long as the datasetup and hold times are not violated. A LOW logic level onthe preset or clear inputs will set or reset the outputsregardless of the logic levels of the other inputs.

Ordering Code:

Order NumberDM7474MDM7474NPackage Number

M14AN14APackage Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WideDevices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection DiagramFunction Table

Inputs

PRLHLHHH

CLRHLLHHH

CLKXXX↑↑L

DXXXHLX

OutputsQHL

QLH

HH(Note 1)(Note 1)HLQ0

LHQ0

H = HIGH Logic Level

X = Either LOW or HIGH Logic LevelL = LOW Logic Level

↑ = Positive-going transition of the clock.

Q0 = The output logic level of Q before the indicated input conditions were

established.Note 1: This configuration is nonstable; that is, it will not persist when eitherthe preset and/or clear inputs return to their inactive (HIGH) level.

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DM7474Absolute Maximum Ratings(Note 2)

Supply VoltageInput Voltage

Operating Free Air Temperature RangeStorage Temperature Range

7V5.5V

0°C to +70°C−65°C to +150°C

Note 2: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.

Recommended Operating Conditions

SymbolVCCVIHVILIOHIOLfCLKtW

Parameter

Supply VoltageHIGH Level Input VoltageLOW Level Input VoltageHIGH Level Output CurrentLOW Level Output CurrentClock Frequency (Note 4)Pulse Width(Note 4)

Clock HIGHClock LOWClear LOWPreset LOW

tSUtHTA

Input Setup Time (Note 3)(Note 4)Input Hold Time (Note 3)(Note 4)Free Air Operating Temperature03037303020↑5↑070nsns°Cns

Min4.752

0.8−0.41615

Nom5Max5.25UnitsVVVmAmAMHz

Note 3: The symbol (↑) indicates the rising edge of the clock pulse is used for reference.Note 4: TA = 25°C and VCC = 5V.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)SymbolVIVOHVOLIIIIH

Parameter

Input Clamp VoltageHIGH Level Output VoltageOutput Voltage

Input Current @ Max Input VoltageHIGH Level Input Current

Conditions

VCC = Min, II = −12 mAVCC = Min, IOH = MaxVIL = Max, VIH = MinVIH = Min, VIL = MaxVCC = Max, VI = 5.5VVCC = MaxVI = 2.4V

DClockClearPreset

IIL

LOW Level VCC = MaxInput Current

VI = 0.4V(Note 8)

IOSICC

Short Circuit Output CurrentSupply Current

VCC = Max (Note 6)VCC = Max (Note 7)

DClockClearPreset

−18

17

2.4

3.40.2

0.41408012040−1.6−3.2−3.2−1.6−5530

mAmAmAµA

Min

Typ(Note 5)

Max−1.5

UnitsVVVmA

LOW Level VCC = Min, IOL = Max

Note 5: All typicals are at VCC = 5V, TA = 25°C.

Note 6: Not more than one output should be shorted at a time.

Note 7: With all outputs open, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.Note 8: Clear is tested with preset HIGH and preset is tested with clear HIGH.

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DM7474Switching Characteristics

at VCC = 5V and TA = 25°C

SymbolfMAXtPHLtPLHtPHLtPLHtPHLtPLH

Parameter

Maximum ClockFrequency

Propagation Delay TimeHIGH-to-LOW Level OutputPropagation Delay TimeLOW-to-HIGH Level OutputPropagation Delay TimeHIGH-to-LOW Level OutputPropagation Delay TimeLOW-to-HIGH Level OutputPropagation Delay TimeHIGH-to-LOW Level OutputPropagation Delay TimeLOW-to-HIGH Level Output

Preset to QPreset to QClear to QClear to QClock to Q or QClock to Q or QFrom (Input)To (Output)

RL = 400Ω, CL = 15 pFMin15

402540254025Max

UnitsMHznsnsnsnsnsns

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DM7474Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M14A

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DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.

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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

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