H桥电机驱动2253

Full-Bridge Power MOSFET Controller

Not for New Design

The A3940KLPTR-T variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available.

Date of status change: April 30, 2007

Recommended Substitutions:

For existing customer transition, and for new customers or new appli-cations, refer to the A3941.

NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

3940The A3940KLP and A3940KLW are designed specifi cally for

automotive applications that require high-power motors. Each provides four high-current gate drive outputs capable of driving a wide range of n-channel power MOSFETs in a full-bridge confi guration. Bootstrap capacitors are utilized to provide the above-battery supply voltage required for n-channel FETs. An internal charge pump for the high side allows for dc (100% duty cycle) operation of the bridge. Protection features include supply under/overvoltage, thermal shut-down, and motor lead short-to-battery and short-to-ground fault notifi -cation, and a programmable dead-time adjustment for cross-conduction prevention. The overvoltage trip point is user adjustable.

The A3940 is supplied in a choice of two power packages, a 28-pin TSSOP with an exposed thermal pad (package type LP), and a 28-pin wide-body SOIC (package type LW). Both package types are available in lead (Pb) free versions, with 100 % matte-tin leadframe plating (suf-fi x –T).

Data Sheet29319.100JA3940KLP(TSSOP with exposed thermal pad)A3940KLW(SOIC)Approx. 2X actual size.ABSOLUTE MAXIMUM RATINGSLoad Supply Voltage Range, VBB, VD-RAIN, CP1 ........................ -0.6 V to +40 VOutput Voltage Ranges,LSS .............................. -2 V to +6.5 VGHA/GHB, VGHX ......... -2 V to +55 VSA/SB, VSX .................. -2 V to +45 VGLA/GLB, VGLX .......... -2 V to +16 VCA/CB, VCX .............. -0.6 V to +55 VCP2,VCP, VIN ........... -0.6 V to +52 VLogic Input/Output Voltage RangeVIN, VOUT .................... -0.3 V to +6.5 VOperating Temperature Range, TA ............................ -40°C to +135°CJunction Temperature, TJ .......... +150°C*Storage Temperature Range, TS ............................ -55°C to +150°C* Fault conditions that produce excessive junc-tion temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. FEATURESDrives wide range of n-channel MOSFETsCharge pump to boost gate drive at low-battery-input conditionsBootstrapped gate drive with charge pump for 100% duty cycleSynchronous rectifi cationFault diagnostic outputAdjustable dead-time cross-conduction protection

 Motor lead short-to-battery and short-to-ground protection Undervoltage/overvoltage protection -40°C to +150°C, TJ operation Thermal shutdown

Always order by complete part numberPart Number

A3940KLPTR

Pb-free

–

Status Package

NND LTB

28-pin TSSOP 28-pin TSSOP

Packing

4000 pcs/reel 4000 pcs/reel

A3940KLPTR-T Yes

3940FULL-BRIDGE POWERMOSFET CONTROLLER

Functional Block Diagram

See pages 7 and 8 for terminal assignments and descriptions.

115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000Copyright © 2003 Allegro MicroSystems, Inc.23940FULL-BRIDGE POWERMOSFET CONTROLLER

A3940KLP (TSSOP)A3940KLW (SOIC)

* Measured on “High-K” multi-layer PWB per JEDEC Standard JESD51-7.† Measured on typical two-sided PWB .

The products described here are manufactured under one or moreU.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time totime, such departures from the detail specifications as may be requiredto permit improvements in the performance, reliability, or

manufacturability of its products. Before placing an order, the user iscautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical componentsin life-support devices or systems without express written approval.The information included herein is believed to be accurate andreliable. However, Allegro MicroSystems, Inc. assumes no responsi-bility for its use; nor for any infringement of patents or other rights ofthird parties which may result from its use.

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3940FULL-BRIDGE POWERMOSFET CONTROLLER

VIN ≤ VBB = 7 V to 40 V, Cp = 0.47 µF, Cr = 1 µF, CREG5 = 0.1 µF, CREG13 = 10 µF, CBOOT = 0.1 µF, PWM = 22.5 kHzsquare wave.

CharacteristicsPower SupplyVBB Quiescent Current

IBB

RESET = 1, VBB = VIN = 40 V, VIN ≠ VCP,

coast, stopped, CP disabled, IDEAD = 170 µARESET = 1, VBB = VIN = 15 V, VIN ≠ VCP,coast, stopped, CP disabled, IDEAD = 170 µARESET = 1, VBB = VIN = 40 V, VIN ≠ VCP, coast, stopped, IDEAD = 170 µA, ICP = 0 mA

RESET = 1, VBB = VIN = 15 V, VIN ≠ VCP, coast,stopped, IDEAD = 170 µA, ICP = 0 mA

RESET = 1, VBB = VIN = 40 V, VIN ≠ VCP, coast, stopped, IDEAD = 170 µA, ICP = 15 mA

RESET = 1, VBB = VIN = 15 V, VIN ≠ VCP, coast,stopped, IDEAD = 170 µA, ICP = 15 mARESET = 0No load

IREG5 = 4.0 mA

IREG5 = 0 - 4.0 mA, VBB = 40 VVBB = 40 V, VREG5 = 0

VBB = 14 - 40 V, ICP = 15 mAVBB = 7 V, ICP = 15 mA

SR = 1, MODE = 0, ENABLE = PWMICP = 15 mA, VBB = 14 V - 40 VVIN = VCP, VBB = 14 V - 40 VVIN = VCP, VBB = 7 V

RESET = 1, VBB = VIN = 40 V, coast, stoppedVIN = 15 V, no load

IREG13 = 15 mA, VIN = 11 V - 14 VVIN = 15 V - 40 V, IREG13 = 15 mAVIN = 40 V, IREG13 = 0 - 15 mAVIN = 40 V, VREG13 = 0 (pulse)RESET = 0 to VREG5 = 4 V

RESET = 1 to VREG13, UV cleared

–––––––4.5–––11.715––––12.6––––10 –

4.84.35.04.835.435.1–5.05.05.02813–5002.53.51.413.30.72.02.060301.4

7.07.07.07.040.040.01.05.5–––13.8–––––14.0––––––

Symbol

Conditions

Min

LimitsTypMax

ELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = -40°C to +135°C, TJ = -40°C to +150°C,

UnitsmAmAmAmAmAmAµA

VmVmVmAVVmAmVmsmsmAVVmVmVmAµsms

VREG5 Output VoltageVREG5 Line RegulationVREG5 Load RegulationVREG5 Short-Circuit CurrentVCP Output Voltage LevelVCP Gate Drive

VCP Output Voltage RippleVCP Pump-Up time

VREG13 Quiescent Input CurrentVREG13 Output VoltageVREG13 Dropout VoltageVREG13 Line RegulationVREG13 Load RegulationVREG13 Short-Circuit CurrentGo-to-Sleep Response TimeWake-Up Response Time

VREG5VREG5VREG5IREG5MVCPICPVCP(PP)tupIREG13VREG13VREGDVVREG13VREG13IREG13Mtsleeptwake

VBB+9.5VBB+10.7 VBB+11.8NOTES:Typical Data is for design information only.

Negative current is defined as coming out of (sourcing) the specified device terminal.

Continued next page …

4115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003940FULL-BRIDGE POWERMOSFET CONTROLLER

VIN ≤ VBB = 7 V to 40 V, Cp = 0.47 µF, Cr = 1 µF, CREG5 = 0.1 µF, CREG13 = 10 µF, CBOOT = 0.1 µF, PWM = 22.5 kHzsquare wave.CharacteristicsControl LogicLogic Input VoltageVIN(1)VIN(1)VIN(0)IIN(1)IIN(0)IIN(0)VDSL(H)IxUrSDU(on)trVDSL(L)IxLrDSL(on)tftpdtsk(o)tdeadHIGH level input (Logic 1), except RESET.HIGH level input (Logic 1) for RESETLOW level input (Logic 0)VIN = 2.0 VVIN = 0.8 V, except RESET(0)VIN = 0.8 V, RESET(0)GHx: IxU = -10 mA, Vsx = 0GLx: IxU = -10 mA, Vlss = 0VSDU = 10 V, TJ = 25°CVSDU = 10 V, TJ = 135°CIxU = -150 mA, TJ = 25°CIxU = -150 mA, TJ = 135°CMeasure VDSL, 20% to 80%, CL = 3300 pFGHx: IxL = 10 mA, Vsx = 0GLx: IxL = 10 mA, Vlss = 0VDSL = 10 V, TJ = 25°CVDSL = 10 V, TJ = 135°CIxL = +150 mA, TJ = 25°CIxL = +150 mA, TJ = 135°CMeasure VDSL, 80% to 20%, CL = 3300 pFLogic input to unloaded GHx, GLxGrouped by rising or falling edgeLONG = 0, RDEAD = 12.1 kΩ (IDEAD = 167 µA)LONG = 0, RDEAD = 499 kΩ (IDEAD = 4 µA)LONG = 1, RDEAD = 12.1 kΩ (IDEAD = 167 µA)LONG = 1, RDEAD = 499 kΩ (IDEAD = 4 µA)2.02.2–––––––4016–––0.8100401.0VREG13VREG13––1323–150150––6.07.5–22550–11.0–345SymbolConditionsMinLimitsTypMaxELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = -40°C to +135°C, TJ = -40°C to +150°C,

UnitsVVVµAµAµAVVmAmAΩΩnsmVmVmAmAΩΩnsnsnsµsµsµsµsLogic Input CurrentGate Drives, GHx, GLx ( internal SOURCE or upper switch stages)Output High Voltage Source Current (pulsed)Source ON ResistanceSource Load Rise TimeOutput Low VoltageSink Current (pulsed)Sink ON ResistanceSink Load Fall TimeGate Drives, GHx, GLx (General)Propagation DelayOutput Skew TimeDead Time(Shoot-Through Prevention)Between GHx, GLx transitionsof same phase––0.3–8.3–––––––VREG13 - 2.2–VREG13 - 0.2––700400–4.0–7.0––90–––5501.83.0–––800–––70Gate Drives, GHx, GLx ( internal SINK or lower switch stages)NOTES:Typical Data is for design information only.

Negative current is defined as coming out of (sourcing) the specified device terminal.For GHX: VSDU = VCX – VGHX, VDSL = VGHX – VSX, VDSL(H) = VCX – VSDU – VSX.

For GLX: VSDU = VREG – VGLX, VDSL = VGLX – VLSS, VDSL(H) = VREG – VSDU – VLSS.

Continued next page …

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3940FULL-BRIDGE POWERMOSFET CONTROLLER

VIN ≤ VBB = 7 V to 40 V, Cp = 0.47 µF, Cr = 1 µF, CREG5 = 0.1 µF, CREG13 = 10 µF, CBOOT = 0.1 µF, PWM = 22.5 kHzsquare wave.CharacteristicsBootstrap CircuitDiode Forward Current LimitDiode Forward DropDiode ResistanceTop-off CP Source Current at CxFault LogicVBB UndervoltageVBB Undervoltage HysteresisVREG13 UndervoltageVREG13 Undervoltage Hyst.VBB OvervoltageVBB(uv)∆VBB(uv)VREG13(uv)∆VREG13(uv)VBB(ov)Decreasing VBBVBB(recovery) - VBB(uv)Decreasing VINVREG13(recovery) - VREG13(uv)Increasing VBB, FAULT = 0 to 1, VOVSET = 0 VIncreasing VBB, FAULT = 0 to 1, VOVSET = 0.45 VIncreasing VBB, FAULT = 0 to 1, VOVSET = 0.9 VVBB(ov) - VBB(recovery)0 V < VSET(ov) < 0.9 V0.3 V < VDSTH < 3 VVDSTH = 0.3 VVDSTH = 1.0 VVDSTH = 3.0 VVDSTH = 0.3 VVDSTH = 1.0 VVDSTH = 3.0 VIf VDRAIN < VDO(th), FAULT = 0 to 1RESET = 0RESET = 1, VDSTH < 3 VRESET = 0, pulseFrom RESET = 1 to FAULT = 0Iout = 5 mA, faults negatedVout = 5 V, open-drain, fault assertedTJ increasingTJ decreasing4.52007.5200162432.52.1––VDSTH-0.14VDSTH-0.18VDSTH-0.39VDSTH-0.20VDSTH-0.24VDSTH-0.371.0––0.15––––––5.2508.25019.62836.43.1––––––––––––2.01.7––172126.07009.07002230.5394.11.41.0VDSTH+0.10VDSTH+0.13VDSTH+0.26VDSTH+0.30VDSTH+0.30VDSTH+0.303.01.05002.0––0.41.0––ICXVFRFIcx3 V < [(VREG13 = 13.5 V) - VCX] < 12 VIF = 10 mARF(100) = [VF(150) - VF(50)]/100VCX - VSX = 8 V, VBB = 40 V, GHx = 1(no load)1400.81.0––––10002.06.5–SymbolConditionsMinLimitsTypMaxELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = -40°C to +135°C, TJ = -40°C to +150°C,

UnitsmAVΩµAVmVVmVVVVVµAµAVVVVVVVµAµAµsµsµsVµA°C°CVBB Overvoltage HysteresisOVSET Input CurrentVDSTH Input CurrentShort-to-Ground Threshold∆VBB(ov)ISET(ov)IDSTHVSTG(th)yShort-to-Battery ThresholdVSTB(th)VDRAIN /Open Bridge ThresholdVDRAIN /Open Bridge CurrentFault Latch Clear PulsewidthFault Clear Propagation DelayFault Detection Noise FilterFault OutputThermal Shutdown TemperatureThermal Shutdown HysteresisVDO(th)IVDRAINtlatchtpdtnoiseVout(0)Iout(1)TJ∆TJNOTES:Typical Data is for design information only.

Negative current is defined as coming out of (sourcing) the specified device terminal.

6115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003940FULL-BRIDGE POWERMOSFET CONTROLLER

Terminal Functions

Terminal Name

VDRAINLSSGLBSBGHBCBVINVREG13CAGHASAGLAVBBCP2VCPCP1GNDFAULTOVSETVREG5MODESRENABLEPHASERESETLONGIDEADVDSTH

Function

Kelvin connection to MOSFET high-side drainsGate-drive source return, low-sideGate-drive B output, low-sideMotor phase B input

Gate-drive B output, high-sideBootstrap capacitor B

Regulated 13 V gate drive supply inputRegulated 13 V gate drive supply outputBootstrap A capacitorGate-drive A output, high-sideMotor phase A inputGate-drive A output, low-sideBattery supply

Charge pump connection for pumping capacitorCharge pump output

Charge pump connection for pumping capacitor

Common ground and dc supply returns

Electrically connected to exposed thermal pad of LP packageOpen-drain fault output

DC input, overvoltage threshold setting for VBBRegulated 5 V supply outputControl inputControl inputControl inputControl inputControl input

Control input, long or short deadtimeAdjust current for basic deadtime

DC input, drain-to-source monitor threshold voltage

TerminalNumber

123456710111213141516171819202122232425262728

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3940FULL-BRIDGE POWERMOSFET CONTROLLER

Terminal Descriptions

CA/CB. High-side connection for bootstrap capacitor, positivesupply for high-side gate drive. The bootstrap capacitor ischarged to VREG13 – 1.5 V when the output Sx terminal is low.When the output swings high, the voltage on this terminal riseswith the output to provide the boosted gate voltage needed for n-channel power MOSFETs.

RESET. Control input to put device into minimum powerconsumption mode and to clear latched faults. Logic “1”

enables the device; logic “0” triggers the sleep mode. Internallypulled down via 50 kΩ resistor.

ENABLE. Logic “1” enables direct control of the output

drivers via the PHASE input, as in PWM controls, and ignoresthe MODE and SR inputs. Internally pulled down via 50 kΩresistor.

MODE. Logic input to set the current decay mode. Logic “1”(slow-decay mode) switches off the high-side MOSFET inresponse to a PWM “off” command. Logic “0” (fast-decaymode) switches off both the high-side and low-side MOSFETs.Internally pulled down via 50 kΩ resistor.

PHASE. Motor direction control. When logic “1”, enablesgate drive outputs GHA and GLB allowing current flow fromSA to SB. When logic “0”, enables GHB and GLA allowingcurrent flow from SB to SA. Internally pulled down via 50 kΩresistor.

SR. When logic “1”, enables synchronous rectification; logic“0” disables the synchronous rectification. Internally pulleddown via 50 kΩ resistor.

FAULT. Open drain, diagnostic logic output signal. Whenlogic “1”, indicates that one or more fault conditions have

occurred. Use an external pullup resistor to VREG5 or to digitalcontroller. Internally causes a coast when asserted. See alsoFunctional Description, next page.

IDEAD. Analog current set by resistor (12 kΩMOSFET drivers. External series gate resistors can control slewrate seen at the power driver gate.

GLA/GLB. Low-side gate drive outputs for external, n-channelMOSFET drivers. External series gate resistors can control slewrate seen at the power driver gate.

GND. Common ground and dc supply returns. Exposedthermal pad of LP package is NOT internally connected toGND.

LSS. Low-side gate drivers’ return. Connects to the commonsources in the low-side of the power MOSFET bridge. It is thereference connection for the short-to-battery monitor.

OVSET. A positive, dc level that controls the VBB overvoltagetrip point. Usually, provided from precision resistor dividernetwork between VREG5 and GND. If connected directly toVREG5, sets unspecified but high overvoltage trip point, effec-tively eliminating the overvoltage protection.

SA/SB. Directly connected to the motor terminals, theseterminals sense the voltages switched across the load and areconnected to the negative side of the bootstrap capacitors. Also,are the negative supply connection for the floating, high-sidedrivers.

VBB. Positive supply voltage. Usually connected to the motorvoltage supply. If VBB is above a specified level or below aspecified level, a fault will be asserted.

VDRAIN. Kelvin connection for drain-to-source voltage (short-to-ground) monitor and is connected to high-side drains of theMOSFET bridge. Also used to detect “open drain”.

VDSTH. A positive, dc level that sets the short-to-ground andshort-to-battery monitor threshold voltage. If the drain-sourcevoltage exceeds this level (after the dead time) during an “on”state, a fault will be asserted.

CP1 [CP2]. Charge pump capacitor negative [positive] side. Ifnot using the charge pump, leave both terminals open.VCP. Charge pump output for VREG13 input. If not using thecharge pump, connect this terminal to VBB.

VIN. Positive supply voltage for the VREG13 linear regulator.Usually connected to VCP, the charge-pump output gate drive.If not using the charge pump, connect VIN to VBB or other dcsupply greater than 11 V.

VREG13. High-side, gate-driver supply. If VREG13 falls belowa specified level, a fault will be asserted.VREG5. Regulated 5 V output for internal logic.

8115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003940FULL-BRIDGE POWERMOSFET CONTROLLER

Functional Description

Motor Lead Protection. A fault detection circuit monitorsthe voltage across the drain to source of the external MOSFETs.A fault is asserted “high” on the output terminal, FAULT, if thedrain-to-source voltage of any MOSFET that is instructed to turnon is greater than the voltage applied to the VDSTH input terminal.When a high-side switch is turned on, the voltage from VDRAIN tothe appropriate motor phase output, VSX, is examined. If themotor lead is shorted to ground the measured voltage willexceed the threshold and the FAULT terminal will go “high”.Similarly, when a low-side MOSFET is turned on, the differen-tial voltage between the motor phase (drain) and the LSS

terminal (source) is monitored. VDSTH is set by a resistor dividerto VREG5.

To prevent erroneous motor faults during switching, thefault circuitry will wait two dead times after every PWM/phasechange before monitoring the drain-to-source voltage; except, itwill use one dead time for (1) a long coast to any phase on, or(2) a long hi-Z before on for that phase. This allows time for themotor output voltage to settle before checking for motor faultwhen using slow rise/fall gate-control waveforms.

The VDRAIN is intended to be a Kelvin connection for thehigh-side, drain-source monitor circuit. Voltage drops acrossthe power bus are eliminated by connecting an isolated PCBtrace from the VDRAIN terminal to the drain of the MOSFETbridge. This allows improved accuracy in setting the VDSTH

threshold voltage. The low-side, drain-source monitor uses theLSS terminal, rather than VDRAIN, in comparing against VDSTH.Fault States. The FAULT terminal provides real time

indication of fault conditions after some digital noise filtering.The VDRAIN fault acts as if a short-to-ground fault existed onevery motor phase. Bridge (or motor) faults are latched but

cleared by a RESET = 0 pulse or by power cycling. GHx = GLx= 0 during RESET = 0. The undervoltage, overvoltage, andthermal shutdown faults are not latched and will not reset untilthe cause is eliminated. All faults cause, via the FAULT line, acoast and some cause shutdown of the regulators, as in the FaultResponses table (next page).

Note: As a test mode, if the thermal shutdown or SLEEP has notoccurred and the FAULT output is externally held low, the coastmode and regulator shutdowns will not occur if motor or voltagefaults occur. Do not wire-OR this terminal to other FAULTlines.

Dead Time. The A3940 is intended to drive a wide range ofpower MOSFETs in applications requiring a wide range ofswitching times. In order to prevent cross conduction (a.k.a.shoot-through) during direction and PWM changes, a powerMOSFET must be turned off before its “phase-pin mate” isturned on.

tDEAD(ns) = K([18.8RDEAD(kΩ)] + 50) + 90

where K = 1 for LONG = 0; K = 32 for LONG = 1.

Note: IDEAD(mA) ≈ 2/RDEAD(kΩ), 12 kΩcircuits. The user should wait the pump-up time, tup, to allow thedevice to be powered up properly before a gate output is

enabled. Please refer to power-up diagram in application noteAN295040 for more detail.Charge Pump. The A3940 is designed to accommodate awide range of power supply voltages. The charge pump outputvoltage, VCP, is regulated to VBB + 11 V (or about 2VBB ifVBB < 11 V).

VREG13. A 13.3 V, low-dropout, linear regulator is used topower the low-side gate drive circuit directly and to provide thecurrent to charge the bootstrap capacitors for the high-side gatedrive. The input supply connection to this regulator, VIN, canbe externally connected to the charge pump output, VCP, or itcan be directly connected to the VBB or VBAT terminal.Internal current limiting protects VREG13.

VREG5. A 5 V, low-dropout, linear regulator is used to powerthe internal logic, regulators, and thermal detection. This

regulator can also power low-current external resistor networksfor VDSTH and OVSET, and the FAULT output pull-up. Theinput supply connection is VBB. Internal current limitingprotects VREG5.

Power-Up State. If the input logic is open, internal pull-downs put the system in coast mode on powering up. First, issuea brake command for >10 µs to charge the bootstrap capacitorsand avoid a possible short-to-ground fault indication.

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3940FULL-BRIDGE POWERMOSFET CONTROLLER

Functional Description (cont’d)

Control Logic

PHASEENABLEMODE00000

10000

X0101

SRX1100

GLA10101

GLB01100

GHA01000

GHB10000

SALoHiLoZLo

SBHiLoLoZZ

Mode of OperationReverse

Fast decay, SR enabledSlow decay, braking modeFast decay, coast

Slow decay, SR disabled

11XX0110HiLoForward10011001LoHiFast decay, SR enabled10111100LoLoSlow decay, braking mode10000000ZZFast decay, coast1 0 1 0 0 1 0 0 Z Lo Slow decay, SR disabled

NOTES:All faults will coast the motor, i.e., GHA = GHB = GLA = GLB = 0 to switch off all bridge MOSFETs.X = Indicates a “don’t care”.

Z = Indicates a high-impedance state.

Fault Responses

Fault Mode

No Fault

Short-to-Battery\"#Short-to-Ground\"$

Open Bridge (VDRAIN)\"%VREG13 UndervoltageVBB OvervoltageVBB UndervoltageThermal ShutdownSleep

RESET111111110

FAULT011111111

CP Reg.ONONONONONONOFFOFFOFF

VREG13ONONONONON&ONOFFOFFOFF

VREG5ONONONONONONON&ON&OFF

GHx–0000'00'0'Z

GLx–0000'00'0'Z

NOTES:\" = These faults are latched but will clear during RESET = 0 pulse. GHx = GLx = 0 during RESET = 0, except see '.

Other faults will not clear except when their cause is removed.

# = Short-to-battery can only be detected when the corresponding GLx = 1.$ = Short-to-ground can only be detected when the corresponding GHx = 1.% = Bridge fault appears as a short-to-ground fault on all motor phases.

& = Not instructed off but may be low voltage because of the fault indicated.

' = During undervoltage conditions, the low sides of GHx and GLx are instructed to be “on” so that the outputs arelow = 0; however, with VREG13 < 4 V, the outputs will start to open (become high impedance). See “Sleep Mode”.

10115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003940FULL-BRIDGE POWERMOSFET CONTROLLER

A3940KLP (TSSOP)

Dimensions in Inches(for reference only)

Dimensions in Millimeters(controlling dimensions)

NOTES:1.Exact body and lead configuration at vendor’s option within limits shown.

2.Lead spacing tolerance is non-cumulative.

3.Supplied in standard sticks/tubes of 50 devices or add “TR” to part number for tape and reel.

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3940FULL-BRIDGE POWERMOSFET CONTROLLER

A3940KLW (SOIC)

Dimensions in Inches(for reference only)

Dimensions in Millimeters(controlling dimensions)

NOTES:1.Lead spacing tolerance is non-cumulative.

2.Exact body and lead configuration at vendor’s option within limits shown.

3.Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.

12115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000