FPGA可编程逻辑器件芯片XC3S2000-4FG900C中文规格书

Figure 76: RX Serial and Parallel Clock Divider

GTYE5_QUAD (GTY Transceiver Primitive)RX PMARXP/NCDRSIPORX DATARX PCSPolarity ControlRX DATA to Downstream PCS BlocksPhase Interp.÷D{1,2,4,8,16}÷{4,5,8,10,16,20}÷{1,2}ILORX PROG DIVHSCLK0/1_RXRECCLKOUT0/110CHCLK_CLKSRCMUX_SELRXOUTPCSCLKRXPHYCLKRXREFCLKPMA÷2001010011101110RX DAPIRX DADIV0CH*_RXOUTCLK1LCPLLHSCLK0/1RPLLRX_DA_REFCLK_SELRXPROGDIVCLKTXOUTCLK_PREDAPIRX DAPIBYPASS DIV10REFCLK SELREFCLK SELRXOUTCLKCTLRX_DA_BYPREFCLK DistributionIBUFDS_GTE5OMGTREFCLKNODIV2Output Clock to BUFG_GTOutput to GTYE5_QUADMGTREFCLKPREFCLK_HROW_CK_SELX21386-031121Notes related to the figure:

1.CH*_RXOUTCLK is used as the source of the interconnect logic clock via BUFG_GT.2.Note that the RPLL and LCPLL from HSCLK0 can only be used by RX channel 0/1, and RPLL

and LCPLL from HSCLK1 can only be used by RX channel 2/3.3.The selection of the /4, /5, /8, /10, /16, and /20 divider block, and the /1 and /2 divider

block is made based on RX_DATA_WIDTH and RX_INT_DATA_WIDTH.4.For details about placement constraints and restrictions on clocking resources (such as

BUFG_GT and BUFG_GT_SYNC), refer to the Versal ACAP Clocking Resources ArchitectureManual (AM003).5.The clock output from IBUFDS_GTE5 should only be used after GTPOWERGOOD asserts

High.

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Chapter 4: Receiver

Serial Clock Divider

Each transmitter PMA module has a D divider that divides down the clock from the PLL for lowerline rate support. This serial clock divider D can be set statically for applications with a fixed linerate or changed dynamically for protocols with multiple line rates.

To use the divider D in fixed line rate applications, RXOUT_DIV must be set to the appropriatevalue, and the CH*_RXRATE port should be tied to 8'b00000000.

For multiple line rate applications, the CH*_TXRATE port is used to dynamically select the linerate settings, which include the appropriate divider values. See Rate Change for more details.

Parallel Clock Divider and Selector

The parallel clock outputs from the RX clock divider control block can be used as an interconnectlogic clock depending on the line rate and protocol requirements.

The recommended clock for the interconnect logic is the CH*_RXOUTCLK from one of the GTYor GTYP transceivers. It is also possible to bring the MGTREFCLK directly to the interconnectlogic and use it as the interconnect logic clock. CH*_RXOUTCLK is preferred for generalapplications because it has an output delay control used for applications that bypass the RXbuffer for constant datapath delay. Refer to RX Buffer Bypass for more details.

The RXOUTCLKCTL attribute controls the input selector and allows these clocks to be output viathe CH*_RXOUTCLK port:

•3'b001: RXOUTCLKPCS path is not recommended to be used because it incurs extra delayfrom the PCS block.•3'b010: RXPHYCLK is the recovered clock that can be brought out to the interconnect logic.The recovered clock is used by protocols that do not have a clock compensation mechanismand require to use a clock synchronous to the data (the recovered clock) to clock the

downstream interconnect logic. It is also used by the RX PCS block. This clock is interruptedwhen the PLL or CDR is reset by one of the related reset signals.•3'b011: RXREFCLKPMA is the input reference clock to the RPLL or LCPLL, depending on theRXOUTCLKCTL setting. For usages that do not require outputting a recovered clock to theinterconnect logic, RXREFCLKPMA can be used as the system clock. However,CH*_TXOUTCLK is usually used as a system clock.•3'b101: RXPRODIVCLK is the divided down PLL clock after the RX programmable divider.See RX Fabric Clock Output Control for more details.•3'b110: TXOUTCLK_PREDAPI is the clock source driving CH*_TXOUTCLK before goingthrough the TX DAPI.

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Versal ACAP GTY and GTYP Transceivers Architecture Manual

Chapter 4: Receiver

RX Programmable Divider

The RX programmable divider shown in RX Fabric Clock Output Control uses the recovered clockfrom the CDR to generate a parallel output clock. By using the recovered clock, RX

programmable divider, and BUFG_GT, CH*_RXOUTCLK (RXOUTCLKCTL = 101) can be used as aclock source for the interconnect logic instead of consuming PLL or MMCM resources in theinterconnect logic. The output clock of the programmable divider can also be brought out to thetransceiver reference clock pin configured as an output. The supported divider values are 4, 5,5.5, 8, 10, 16, 16.5, 20, 32, 33, and 40.

RX DAPI and RX DAPI Bypass Dividers

The RX delay align and phase interpolator (RX DAPI) shown in RX Fabric Clock Output Controlcan either be enabled or bypassed to provide the CH*_RXOUTCLK.

RX_DA_BYP determines the clock path and is set based on application requirements:

•0: The RX DAPI clock path is used to generate the CH*_RXOUTCLK. In this use case, the RXDAPI has a built-in divide-by-2 that is always present. The divider values for RX DA DIVshould be left to the default values from the Wizard example design.•1: The clock path where RX DAPI is bypassed generates the CH*_RXOUTCLK. In this use case,the RX DAPI BYPASS DIV divider value should be left to the default values from the Wizardexample design.

Ports and Attributes

The following table defines the ports required for RX fabric clock output control.Table 88: RX Fabric Clock Output Control Ports

Port

CH[0/1/2/3]_RXOUTCLKCH[0/1/2/3]_RXPROGDIVRESET

Direction

OutputInput

Clock Domain

CLOCKASYNC

Description

RXOUTCLK is the recommended clockoutput to the interconnect logic.

This active-High port resets the dividersas well as the

CH*_RXPROGDIVRESETDONE indicator. Areset must be performed whenever theinput clock source is interrupted.

When the input clock is stable and reset isperformed, this active-High signal

indicates the reset is completed and theoutput clock is stable.

CH[0/1/2/3]_RXPROGDIVRESETDONEOutputASYNC

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Versal ACAP GTY and GTYP Transceivers Architecture Manual