DM74LS166
8-Bit Parallel-In/Serial-Out Shift Register
General Description
These parallel-in or serial-in, serial-out shift registers fea-ture gated clock inputs and an overriding clear input. Allinputs are buffered to lower the drive requirements to onenormalized load, and input clamping diodes minimizeswitching transients to simplify system design. The loadmode is established by the shift/load input. When HIGH,this input enables the serial data input and couples theeight flip-flops for serial shifting with each clock pulse.When LOW, the parallel (broadside) data inputs areenabled and synchronous loading occurs on the next clockpulse. During parallel loading, serial data flow is inhibited.
Clocking is accomplished on the LOW-to-HIGH level edgeof the clock pulse through a two-input NOR gate, permittingone input to be used as a clock-enable or clock-inhibit func-tion. Holding either of the clock inputs HIGH inhibits clock-ing; holding either LOW enables the other clock input. Thisallows the system clock to be free running, and the registercan be stopped on command with the other clock input.The clock-inhibit input should be changed to the high levelonly while the clock input is HIGH. A buffered, direct clearinput overrides all other inputs, including the clock, andsets all flip-flops to zero.
Ordering Code:
Order NumberDM74LS166MDM74LS166WMDM74LS166N
Package Number
M16AM16BN16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
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DM74LS166Function Table
InputsClearLHHHHH
Shift/LoadXXLHHX
ClockInhibitXLLLLH
XL↑↑↑↑
XXXHLX
Clock
Serial
ParallelA…HXXa…hXXX
InternalOutputsQALQA0aHLQA0
QBLQB0bQAnQAnQB0
LQH0hQGnQGnQH0OutputQH
H = HIGH Level (steady state)L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)↑ = Transition from LOW-to-HIGH level
a…h = The level of steady-state input at inputs A through H, respectively
QA0, QB0, QH0 = The level of QA, QB, QH, respectively, before the indicated steady-state input conditions were establishedQAn, QGn, = The level of QA, QG, respectively, before the most recent ↑ transition of the clock
Logic Diagram
Timing Diagram
Typical Clear, Shift, Load, Inhibit and Shift Sequences
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DM74LS166Absolute Maximum Ratings(Note 1)
Supply VoltageInput Voltage
Operating Free Air Temperature RangeStorage Temperature Range
7V7V
0°C to +70°C−65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.
Recommended Operating Conditions
SymbolVCCVIHVILIOHIOLfCLKtWtSUtHTA
Supply VoltageHIGH Level Input VoltageLOW Level Input VoltageHIGH Level Output CurrentLOW Level Output CurrentClock Frequency (Note 2)Clock Frequency (Note 3)Pulse Width (Note 4)Setup Time (Note 4)Hold Time (Note 4)
Free Air Operating TemperatureClockClearModeData
00202030200070Parameter
Min4.752
0.8−0.482520Nom5Max5.25UnitsVVVmAmAMHzMHznsnsns°CNote 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.Note 4: TA = 25°C and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)SymbolVIVOHVOL
Parameter
Input Clamp VoltageHIGH Level Output VoltageOutput Voltage
IIIIHIILIOSICC
Input Current @ Max Input VoltageHIGH Level Input CurrentLOW Level Input CurrentShort Circuit Output CurrentSupply Current
Conditions
VCC = Min, II = −18 mAVCC = Min, IOH = MaxVIL = Max, VIH = MinVIL = Max, VIH = MinIOL = 4 mA, VCC = MinVCC = Max, VI = 7VVCC = Max, VI = 2.7VVCC = Max, VI = 0.4VVCC = Max (Note 6)VCC = Max (Note 7)
−20
22
2.7
3.40.350.25
0.50.40.120−0.4−10038
mAµAmAmAmA
Min
Typ(Note 5)
Max−1.5
UnitsVV
LOW Level VCC = Min, IOL = Max
V
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: With all outputs OPEN, 4.5V applied to the serial input, all other inputs except the CLOCK grounded, ICC is measured after a momentary ground,
then 4.5V is applied to the CLOCK.
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DM74LS166Switching Characteristics
at VCC = 5V and TA = 25°C
From (Input)
SymbolfMAXtPLHtPHLtPHL
Parameter
Maximum Clock FrequencyPropagation Delay TimeLOW-to-HIGH Level OutputPropagation Delay TimeHIGH-to-LOW Level OutputPropagation Delay TimeHIGH-to-LOW Level Output
Clock to OutputClock to OutputClear to OutputTo (Output)
CL = 15 pFMin25886
353530Max
RL = 2 kΩ
CL = 50 pFMin20
384136Max
MHznsnsnsUnits
Parameter Measurement Information
Voltage Waveforms
Test Table for Synchronous Inputs
Data Inputfor TestHSerial Input
0V4.5VShift/Load
Output Tested(See Note C)QH at TN+1QH at TN+8
Note A: The clock pulse has the following characteristics: tW(clock) ≥ 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics:
tW(clear) ≥ 20 ns and tHOLD = 0 ns. When testing fMAX, vary the clock PRR.
Note B: A clear pulse is applied prior to each test.
Note C: Propagation delay times (tPLHand tPHL) are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test.Note D: tn = bit time before clocking transition
tn+1 = bit time after one clocking transitiontn+8 = bit time after eight clocking transitionsNote E: VREF = 1.3V.
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DM74LS166Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M16B
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DM74LS166 8-Bit Parallel-In/Serial-Out Shift RegisterPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.www.fairchildsemi.com
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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
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