CD4094 CMOS 8级移位存储总线寄存器

CD4094BC

8-Bit Shift Register/Latch with 3-STATE Outputs

General Description

The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shiftregister on the positive transition of the clock. The output ofthe last stage (QS) can be used to cascade severaldevices. Data on the QS output is transferred to a secondoutput, Q′S, on the following negative clock edge.

The output of each stage of the shift register feeds a latch,which latches data on the negative edge of the STROBEinput. When STROBE is HIGH, data propagates through

the latch to 3-STATE output gates. These gates areenabled when OUTPUT ENABLE is taken HIGH.

Features

sWide supply voltage range: 3.0V to 18VsHigh noise immunity:

0.45 VDD (typ.)

sLow power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LSs3-STATE outputs

Ordering Code:

Order NumberCD4094BCWMCD4094BCN

Package Number

M16BN16E

Package Description

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Top View

Truth Table

Clock

OutputEnable

Strobe

Data

Parallel OutputsQ1

XX0111XXX011Hi-ZHi-Z01QNHi-ZHi-ZQN−1QN−1

Serial OutputsQS(Note 1)Q7No ChangeQ7Q7Q7

Q′ΣNo ChangeQ7No ChangeNo ChangeNo Change

Q7󰀑󰀐󰀑󰀑󰀑󰀐X = Don't Care

󰀐 = HIGH-to-LOW󰀑 = LOW-to-HIGH

001111No ChangeNo ChangeNo ChangeNo ChangeNo ChangeNote 1: At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.

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CD4094BCBlock Diagram

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CD4094BC Absolute Maximum Ratings(Note 2)

(Note 3)

Supply Voltage (VDD)Input Voltage (VIN)

Storage Temperature Range (TS)Power Dissipation (PD)Dual-In-LineSmall OutlineLead Temperature (TL)(Soldering, 10 seconds)

260°C700 mW500 mW

−0.5 to +18 VDC

−0.5 to VDD +0.5 VDC

−65°C to +150°C

Recommended OperatingConditions (Note 3)

DC Supply Voltage (VDD)Input Voltage (VIN)

Operating Temperature Range (TA)

+3.0 to +15 VDC

0 to VDD VDC−40°C to +85°C

Note 2: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed; they are not meant to imply thatthe devices should be operated at these limits. The tables of “Recom-mended Operating Conditions” and “Electrical Characteristics” provide con-ditions for actual device operation.

Note 3: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

SymbolIDD

QuiescentDevice Current

VOL

LOW LevelOutput Voltage

VOH

HIGH LevelOutput Voltage

VIL

LOW LevelInput Voltage

VIH

HIGH LevelInput Voltage

IOL

LOW LevelOutput Current(Note 4)

IOH

HIGH LevelOutput Current(Note 4)

IINIOZ

Input Current3-STATE OutputLeakage Current

Note 4: IOH and IOL are tested one output at a time.

ParameterConditions

VDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15V

VDD = 5.0V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5VVDD = 5.0V, VO = 0.5V or 4.5VVDD = 10V, VO = 1.0V or 9.0VVDD = 15V, VO = 1.5V or 13.5VVDD = 5.0V, VO = 0.4VVDD = 10V, VO = 0.5VVDD = 15V, VO = 1.5VVDD = 5.0V, VO = 4.6VVDD = 10V, VO = 9.5VVDD = 15V, VO = 13.5VVDD = 15V, VIN = 0VVDD = 15V, VIN = 15VVDD = 15V, VIN = 0V or 15V

|IO| ≤ 1 µA|IO| ≤ 1.0 µA

−40°CMin

Max2040800.050.050.05

4.959.9514.95

1.53.04.0

3.57.011.00.521.33.6−0.52−1.3−3.6

−0.30.31

3.57.011.00.441.13.0−0.44−1.1−3.04.959.9514.95Min

+25°CTyp

Max204080

0005.010.015.0

1.53.04.00.050.050.05

+85°CMin

Max1503006000.050.050.05

4.959.9514.95

1.53.04.0

3.57.011.0

UnitsµAµAµAVVVVVVVVVVVVmAmAmAmAmAmA

0.882.258.80.882.258.8

−0.30.31

0.360.92.4−0.36−0.9−2.4

−1.01.010

µAµAµA

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CD4094BCAC Electrical Characteristics (Note 5)

TA = 25°C, CL = 50 pF

SymboltPHL, tPLH

Parameter

Propagation DelayClock to QS

tPHL, tPLH

Propagation DelayClock to Q′Σ

tPHL, tPLH

Propagation Delay Clockto Parallel Out

tPHL, tPLH

Propagation Delay Strobeto Parallel Out

tPHZ

Propagation Delay HIGHLevel to HIGH Impedance

tPLZ

Propagation Delay LOWLevel to HIGH Impedance

tPZH

Propagation Delay HIGHImpedance to HIGH Level

tPZL

Propagation Delay HIGHImpedance to LOW Level

tTHL, tTLH

Transition Time

VDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15V

tSU

Set-Up TimeData to Clock

tr, tf

Maximum Clock Riseand Fall Time

tPC

Minimum ClockPulse Width

tPS

Minimum StrobePulse Width

fmax

Maximum Clock Frequency

VDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15VVDD = 5.0VVDD = 10VVDD = 15V

CIN

Input Capacitance

Any Input

Note 5: AC Parameters are guaranteed by DC correlated testing.

ConditionsMinTyp300125952301107542019513529014510014075551407555140755514075551005040

Max60025019046022015084039027058029020028015011028015011028015011028015011020010080

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsmsms

8040201112001008320080701.53.04.0

402010

100504010040353.06.08.05.0

7.5

nsnsnsnsnsnsMHzMHzMHzpF

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CD4094BC Timing Diagram

Test Circuits and Timing Diagrams for 3-STATE

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CD4094BCPhysical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

M16B

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CD4094BC 8-Bit Shift Register/Latch with 3-STATE OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

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2.A critical component in any component of a life support1.Life support devices or systems are devices or systems

device or system whose failure to perform can be rea-which, (a) are intended for surgical implant into the

sonably expected to cause the failure of the life supportbody, or (b) support or sustain life, and (c) whose failure

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instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to thewww.fairchildsemi.comuser.

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.